Software Library API naibrd 2.24.0
See all documentation at naii.docs.com
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Functions | |
NAIBRDFUNC nai_status_t NAIAPI | naibrd_AD_GetFIFOCount (int32_t cardIndex, int32_t module, int32_t channel, uint32_t *p_outcount) |
Retrieves the FIFO counter registers that indicate the number of data elements in the A/D channel's FIFO buffer. Each time a read operation is made to the A/D channel's FIFO Buffer, the corresponding FIFO counter register is decremented by one. The maximum number of items that can be stored in each A/D channel's FIFO is 26,213 (0x6665). The maximum number of items that can be stored in each gen5 A/D channel's FIFO is 2,097,151 (0x001FFFFF). | |
NAIBRDFUNC nai_status_t NAIAPI | naibrd_AD_ReadFIFORaw32 (int32_t cardIndex, int32_t module, int32_t channel, uint32_t count, uint32_t p_outdata[], uint32_t *p_outread) |
Retrieves data elements from the A/D channel's FIFO buffer. The data is presented in two's complement format. For bipolar mode; 0x7FFF equals Positive Full Scale, 0x8000 equals Negative Full Scale. For unipolar mode, the range is from 0x0000 to 0xFFFF where 0xFFFF equals Full Scale. | |
NAIBRDFUNC nai_status_t NAIAPI | naibrd_AD_ReadFIFO (int32_t cardIndex, int32_t module, int32_t channel, uint32_t count, float64_t p_outdata[], uint32_t *p_outread) |
Retrieves data elements from the A/D channel's FIFO buffer. The data is retrieved in two's complement format, and is then converted into floating-point format. If floating-point mode is enabled for the module, the data will be converted into IEEE 754 (32-bit) floating-point format. If floating-point mode is disabled, the data is converted into floating-point format based on the following specifications: For bipolar mode; 0x7FFF equals Positive Full Scale, 0x8000 equals Negative Full Scale. For unipolar mode, the range is from 0x0000 to 0xFFFF where 0xFFFF equals Full Scale. Full Scale is the maximum value of the range. | |
NAIBRDFUNC nai_status_t NAIAPI | naibrd_AD_SetFIFOAlmostEmpty (int32_t cardIndex, int32_t module, int32_t channel, uint32_t empty) |
Sets the almost empty mark to use to set or reset the A/D channel's FIFO Status "Almost Empty" bit. When the A/D channel's FIFO counter is less than or equal to the almost empty mark, the "Almost Empty" bit will be set. When the A/D channel's FIFO counter is greater than the almost empty mark, the "Almost Empty" bit will be reset. | |
NAIBRDFUNC nai_status_t NAIAPI | naibrd_AD_GetFIFOAlmostEmpty (int32_t cardIndex, int32_t module, int32_t channel, uint32_t *p_outempty) |
Retrieves the "almost empty" mark used to set or reset the A/D channel's FIFO Status "Almost Empty" bit. When the A/D channel's FIFO counter is less than or equal to the "almost empty" mark, the "Almost Empty" bit will be set. When the A/D channel's FIFO counter is greater than the "almost empty" mark, the "Almost Empty" bit will be reset. | |
NAIBRDFUNC nai_status_t NAIAPI | naibrd_AD_SetFIFOAlmostFull (int32_t cardIndex, int32_t module, int32_t channel, uint32_t full) |
Sets the almost full mark to use to set or reset the A/D channel's FIFO Status "Almost Full" bit. When the A/D channel's FIFO counter is less than or equal to the almost full mark, the "Almost Full" bit will be set. When the A/D channel's FIFO counter is greater than the almost full mark, the "Almost Full" bit will be reset. | |
NAIBRDFUNC nai_status_t NAIAPI | naibrd_AD_GetFIFOAlmostFull (int32_t cardIndex, int32_t module, int32_t channel, uint32_t *p_outfull) |
Retrieves the "almost full" mark used to set or reset the A/D channel's FIFO Status "Almost Full" bit. When the A/D channel's FIFO counter is less than or equal to the "almost full" mark, the "Almost Full" bit will be set. When the A/D channel's FIFO counter is greater than the "almost full" mark, the "Almost Full" bit will be reset. | |
NAIBRDFUNC nai_status_t NAIAPI | naibrd_AD_SetFIFOLoThreshold (int32_t cardIndex, int32_t module, int32_t channel, uint32_t threshold) |
Sets the low threshold level to use to set or reset the A/D channel's FIFO Status "Low Limit" bit. When the A/D channel's FIFO counter is less than or equal to the low threshold level, the "Low Limit" bit will be set. When the A/D channel's FIFO counter is greater than the low threshold level, the "Low Limit" bit will be reset. | |
NAIBRDFUNC nai_status_t NAIAPI | naibrd_AD_GetFIFOLoThreshold (int32_t cardIndex, int32_t module, int32_t channel, uint32_t *p_outthreshold) |
Retrieves the low threshold level to use to set or reset the A/D channel's FIFO Status "Low Limit" bit. When the A/D channel's FIFO counter is less than or equal to the low threshold level, the "Low Limit" bit will be set. When the A/D channel's FIFO counter is greater than the low threshold level, the "Low Limit" bit will be reset. | |
NAIBRDFUNC nai_status_t NAIAPI | naibrd_AD_SetFIFOHiThreshold (int32_t cardIndex, int32_t module, int32_t channel, uint32_t threshold) |
Sets the high threshold level to use to set or reset the A/D channel's FIFO Status "High Limit" bit. When the A/D channel's FIFO counter is greater than or equal to the high threshold level, the "High Limit" bit will be set. When the A/D channel's FIFO counter is less than the high threshold level, the "High Limit" bit will be reset. | |
NAIBRDFUNC nai_status_t NAIAPI | naibrd_AD_GetFIFOHiThreshold (int32_t cardIndex, int32_t module, int32_t channel, uint32_t *p_outthreshold) |
Retrieves the high threshold level to use to set or reset the A/D channel's FIFO Status "High Limit" bit. When the A/D channel's FIFO counter is greater than or equal to the high threshold level, the "High Limit" bit will be set. When the A/D channel's FIFO counter is less than the high threshold level, the "High Limit" bit will be reset. | |
NAIBRDFUNC nai_status_t NAIAPI | naibrd_AD_SetFIFODelay (int32_t cardIndex, int32_t module, int32_t channel, uint32_t delay) |
Sets the number of delay samples before the actual FIFO data collection begins. The data collected during the delay period will be discarded. | |
NAIBRDFUNC nai_status_t NAIAPI | naibrd_AD_GetFIFODelay (int32_t cardIndex, int32_t module, int32_t channel, uint32_t *p_outdelay) |
Retrieves the number of delay samples before the actual FIFO data collection begins. The data collected during the delay period will be discarded. | |
NAIBRDFUNC nai_status_t NAIAPI | naibrd_AD_SetFIFOSize (int32_t cardIndex, int32_t module, int32_t channel, uint32_t size) |
Sets the number of samples to be taken and placed into the FIFO before the A/D channel's FIFO Status "Sample Done" bit is set after a trigger occurs. Note that the size of each sample (number of words written to the FIFO per sample) is determined by the sample format described by the Buffer Control register. | |
NAIBRDFUNC nai_status_t NAIAPI | naibrd_AD_GetFIFOSize (int32_t cardIndex, int32_t module, int32_t channel, uint32_t *p_outsize) |
Retrieves the number of samples to be taken and placed into the FIFO before the A/D channel's FIFO Status "Sample Done" bit is set after a trigger occurs. Note that the size of each sample (number of words written to the FIFO per sample) is determined by the sample format described by the Buffer Control register. | |
NAIBRDFUNC nai_status_t NAIAPI | naibrd_AD_SetFIFOSkip (int32_t cardIndex, int32_t module, int32_t channel, uint32_t skip) |
Sets the skip count for the FIFO buffer. The FIFO skip count sets how many samples to skip over in between each FIFO store. For example, if the sample rate for a channel is 10kHz, there would be a new sample every 100 micro-seconds. By setting the FIFO skip count to 1, the FIFO would store a new sample every 200us, or in other words, at a 5kHz rate. | |
NAIBRDFUNC nai_status_t NAIAPI | naibrd_AD_GetFIFOSkip (int32_t cardIndex, int32_t module, int32_t channel, uint32_t *p_outskip) |
Retrieves the skip count for the FIFO buffer. The FIFO skip count sets how many samples to skip over in between each FIFO store. For example, if the sample rate for a channel is 10kHz, there would be a new sample every 100 micro-seconds. By setting the FIFO skip count to 1, the FIFO would store a new sample every 200us, or in other words, at a 5kHz rate. | |
NAIBRDFUNC nai_status_t NAIAPI | naibrd_AD_SetFIFOCtrl (int32_t cardIndex, int32_t module, int32_t channel, naibrd_ad_fifo_ctrl_t ctrl) |
Sets the format of the samples to be stored in the A/D channel's FIFO buffer. | |
NAIBRDFUNC nai_status_t NAIAPI | naibrd_AD_GetFIFOCtrl (int32_t cardIndex, int32_t module, int32_t channel, naibrd_ad_fifo_ctrl_t *p_outctrl) |
Retrieves the format of the samples to be stored in the A/D channel's FIFO buffer. | |
NAIBRDFUNC nai_status_t NAIAPI | naibrd_AD_ClearFIFO (int32_t cardIndex, int32_t module, int32_t channel) |
Clears the channel's data FIFO. | |
NAIBRDFUNC nai_status_t NAIAPI | naibrd_AD_SetFIFOTrigCtrl (int32_t cardIndex, int32_t module, int32_t channel, naibrd_ad_fifo_trig_t ctrl) |
Sets the A/D channel's FIFO buffer trigger control configuration. | |
NAIBRDFUNC nai_status_t NAIAPI | naibrd_AD_GetFIFOTrigCtrl (int32_t cardIndex, int32_t module, int32_t channel, naibrd_ad_fifo_trig_t *p_outctrl) |
Retrieves the A/D channel's FIFO buffer trigger control configuration. | |
NAIBRDFUNC nai_status_t NAIAPI | naibrd_AD_SoftwareTrigger (int32_t cardIndex, int32_t module) |
Sets the A/D module's FIFO Buffer Software Trigger register to 1. The Software trigger is used to kick start the FIFO buffer and the collection of data. The Trigger Control Configuration for each A/D channel's FIFO must be set up properly before invoking this routine. Setting the Software Trigger will start FIFO data collection for all A/D channels. | |
NAIBRDFUNC nai_status_t NAIAPI naibrd_AD_ClearFIFO | ( | int32_t | cardIndex, |
int32_t | module, | ||
int32_t | channel ) |
Clears the channel's data FIFO.
cardIndex | : (Input) Logical Card Index assigned to connection with the NAI_BOARD (0 - NAI_MAX_CARDS-1). |
module | : (Input) Module Number of the module to access (1 - [max modules for board]). |
channel | : (Input) Channel Number of the channel to access (1 - [max channels for module]). |
NAIBRDFUNC nai_status_t NAIAPI naibrd_AD_GetFIFOAlmostEmpty | ( | int32_t | cardIndex, |
int32_t | module, | ||
int32_t | channel, | ||
uint32_t * | p_outempty ) |
Retrieves the "almost empty" mark used to set or reset the A/D channel's FIFO Status "Almost Empty" bit. When the A/D channel's FIFO counter is less than or equal to the "almost empty" mark, the "Almost Empty" bit will be set. When the A/D channel's FIFO counter is greater than the "almost empty" mark, the "Almost Empty" bit will be reset.
cardIndex | : (Input) Logical Card Index assigned to connection with the NAI_BOARD (0 - NAI_MAX_CARDS-1). |
module | : (Input) Module Number of the module to access (1 - [max modules for board]). |
channel | : (Input) Channel Number of the channel to access (1 - [max channels for module]). |
p_outempty | : (Output) Almost Empty Mark. (module specific range- see spec). |
NAIBRDFUNC nai_status_t NAIAPI naibrd_AD_GetFIFOAlmostFull | ( | int32_t | cardIndex, |
int32_t | module, | ||
int32_t | channel, | ||
uint32_t * | p_outfull ) |
Retrieves the "almost full" mark used to set or reset the A/D channel's FIFO Status "Almost Full" bit. When the A/D channel's FIFO counter is less than or equal to the "almost full" mark, the "Almost Full" bit will be set. When the A/D channel's FIFO counter is greater than the "almost full" mark, the "Almost Full" bit will be reset.
cardIndex | : (Input) Logical Card Index assigned to connection with the NAI_BOARD (0 - NAI_MAX_CARDS-1). |
module | : (Input) Module Number of the module to access (1 - [max modules for board]). |
channel | : (Input) Channel Number of the channel to access (1 - [max channels for module]). |
p_outfull | : (Output) Almost Full Mark. (module specific range- see spec). |
NAIBRDFUNC nai_status_t NAIAPI naibrd_AD_GetFIFOCount | ( | int32_t | cardIndex, |
int32_t | module, | ||
int32_t | channel, | ||
uint32_t * | p_outcount ) |
Retrieves the FIFO counter registers that indicate the number of data elements in the A/D channel's FIFO buffer. Each time a read operation is made to the A/D channel's FIFO Buffer, the corresponding FIFO counter register is decremented by one. The maximum number of items that can be stored in each A/D channel's FIFO is 26,213 (0x6665). The maximum number of items that can be stored in each gen5 A/D channel's FIFO is 2,097,151 (0x001FFFFF).
cardIndex | : (Input) Logical Card Index assigned to connection with the NAI_BOARD (0 - NAI_MAX_CARDS-1). |
module | : (Input) Module Number of the module to access (1 - [max modules for board]). |
channel | : (Input) Channel Number of the channel to access (1 - [max channels for module]). |
p_outcount | : (Output) Number of data elements in FIFO Buffer. |
NAIBRDFUNC nai_status_t NAIAPI naibrd_AD_GetFIFOCtrl | ( | int32_t | cardIndex, |
int32_t | module, | ||
int32_t | channel, | ||
naibrd_ad_fifo_ctrl_t * | p_outctrl ) |
Retrieves the format of the samples to be stored in the A/D channel's FIFO buffer.
GEN3 Bit Format: (LSB) B0 - Data (16-bit High) 16-bit resolution data for unipolar and bipolar A/D data. B1 - Data (8-bit Low) Combined with B0 to form a 24-bit resolution data for unipolar and bipolar A/D data. B2 - Data Type (0 = Raw (unfiltered), 1 = Filtered). B3 - Reserved B4 - Time Stamp An integer counter that counts from 0 to 65,535 and wraps when it overflows. B5 - Reserved B6 - Reserved (MSB) B7 - Reserved Each data format (B0 - B4) requires one data element of storage space from the FIFO buffer. If B0, B1 and B4 are set (0x13), 3 data elements will be written to the FIFO per sample. GEN5 Bit Format: (LSB) B0 - Reserved B1 - Reserved B2 - Data Type (0 = Raw (unfiltered), 1 = Filtered). B3 - Reserved B4 - Time Stamp An integer counter that counts from 0 to 65,535 and wraps when it overflows. B5 - Reserved B6 - Reserved (MSB) B7 - Reserved Sample data requires element of storage space from the FIFO buffer. If B4 is set (0x1X), 2 data elements will be written to the FIFO per sample (1 element is data and 1 element is the timeStamp).
Note, the Fifo Size register should be adjusted to account for the number of data elements placed on the FIFO per sample to prevent an overflow of the FIFO buffer. For eample, if the Fifo Size is set to 1, and the Buffer Control B4 bit is set, an overflow condition will occur after the first sample. When an overflow condition occurs, any un-stored data will be lost. The values in Fifo Size and Buffer Control registers should be set to avoid an overflow of the FIFO buffer.
cardIndex | : (Input) Logical Card Index assigned to connection with the NAI_BOARD (0 - NAI_MAX_CARDS-1). |
module | : (Input) Module Number of the module to access (1 - [max modules for board]). |
channel | : (Input) Channel Number of the channel to access (1 - [max channels for module]). |
p_outctrl | : (Output) FIFO Data Sample Format. |
NAIBRDFUNC nai_status_t NAIAPI naibrd_AD_GetFIFODelay | ( | int32_t | cardIndex, |
int32_t | module, | ||
int32_t | channel, | ||
uint32_t * | p_outdelay ) |
Retrieves the number of delay samples before the actual FIFO data collection begins. The data collected during the delay period will be discarded.
cardIndex | : (Input) Logical Card Index assigned to connection with the NAI_BOARD (0 - NAI_MAX_CARDS-1). |
module | : (Input) Module Number of the module to access (1 - [max modules for board]). |
channel | : (Input) Channel Number of the channel to access (1 - [max channels for module]). |
p_outdelay | : (Output) Number of delay samples before FIFO data collection (0 - 65535 (0xFFFF)). |
NAIBRDFUNC nai_status_t NAIAPI naibrd_AD_GetFIFOHiThreshold | ( | int32_t | cardIndex, |
int32_t | module, | ||
int32_t | channel, | ||
uint32_t * | p_outthreshold ) |
Retrieves the high threshold level to use to set or reset the A/D channel's FIFO Status "High Limit" bit. When the A/D channel's FIFO counter is greater than or equal to the high threshold level, the "High Limit" bit will be set. When the A/D channel's FIFO counter is less than the high threshold level, the "High Limit" bit will be reset.
cardIndex | : (Input) Logical Card Index assigned to connection with the NAI_BOARD (0 - NAI_MAX_CARDS-1). |
module | : (Input) Module Number of the module to access (1 - [max modules for board]). |
channel | : (Input) Channel Number of the channel to access (1 - [max channels for module]). |
p_outthreshold | : (Output) High Threshold Level. (0 - 26,213 (0x6665)). |
NAIBRDFUNC nai_status_t NAIAPI naibrd_AD_GetFIFOLoThreshold | ( | int32_t | cardIndex, |
int32_t | module, | ||
int32_t | channel, | ||
uint32_t * | p_outthreshold ) |
Retrieves the low threshold level to use to set or reset the A/D channel's FIFO Status "Low Limit" bit. When the A/D channel's FIFO counter is less than or equal to the low threshold level, the "Low Limit" bit will be set. When the A/D channel's FIFO counter is greater than the low threshold level, the "Low Limit" bit will be reset.
cardIndex | : (Input) Logical Card Index assigned to connection with the NAI_BOARD (0 - NAI_MAX_CARDS-1). |
module | : (Input) Module Number of the module to access (1 - [max modules for board]). |
channel | : (Input) Channel Number of the channel to access (1 - [max channels for module]). |
p_outthreshold | : (Output) Low Threshold Level. (0 - 26,213 (0x6665)). |
NAIBRDFUNC nai_status_t NAIAPI naibrd_AD_GetFIFOSize | ( | int32_t | cardIndex, |
int32_t | module, | ||
int32_t | channel, | ||
uint32_t * | p_outsize ) |
Retrieves the number of samples to be taken and placed into the FIFO before the A/D channel's FIFO Status "Sample Done" bit is set after a trigger occurs. Note that the size of each sample (number of words written to the FIFO per sample) is determined by the sample format described by the Buffer Control register.
cardIndex | : (Input) Logical Card Index assigned to connection with the NAI_BOARD (0 - NAI_MAX_CARDS-1). |
module | : (Input) Module Number of the module to access (1 - [max modules for board]). |
channel | : (Input) Channel Number of the channel to access (1 - [max channels for module]). |
p_outsize | : (Output) Number of samples before FIFO trigger (0 - 65535 (0xFFFF)). |
NAIBRDFUNC nai_status_t NAIAPI naibrd_AD_GetFIFOSkip | ( | int32_t | cardIndex, |
int32_t | module, | ||
int32_t | channel, | ||
uint32_t * | p_outskip ) |
Retrieves the skip count for the FIFO buffer. The FIFO skip count sets how many samples to skip over in between each FIFO store. For example, if the sample rate for a channel is 10kHz, there would be a new sample every 100 micro-seconds. By setting the FIFO skip count to 1, the FIFO would store a new sample every 200us, or in other words, at a 5kHz rate.
cardIndex | : (Input) Logical Card Index assigned to connection with the NAI_BOARD (0 - NAI_MAX_CARDS-1). |
module | : (Input) Module Number of the module to access (1 - [max modules for board]). |
channel | : (Input) Channel Number of the channel to access (1 - [max channels for module]). |
p_outskip | : (Output) Skip count ( 0 - (0xFFFF FFFF) ). |
NAIBRDFUNC nai_status_t NAIAPI naibrd_AD_GetFIFOTrigCtrl | ( | int32_t | cardIndex, |
int32_t | module, | ||
int32_t | channel, | ||
naibrd_ad_fifo_trig_t * | p_outctrl ) |
Retrieves the A/D channel's FIFO buffer trigger control configuration.
Register Value Trigger Source Slope --------------------------------------------------- 0x20 External Trigger 2 Positive 0x21 External Trigger 1 Positive 0x22 Software Trigger N/A 0x30 External Trigger 2 Negative 0x31 External Trigger 1 Negative 0x32 Software Trigger N/A 0x40 Initiate 0x80 Stop (Clear Trigger) Trigger Configuration Format: (LSB) B0-B1 = Source Select 0x0 = External Trigger 2 0x1 = External Trigger 1 0x2 = Software Trigger B3 = Reserved (MSB) B4-B7 = Trigger Type 0x1X = Negative Slope 0x2X = Trigger Pulse Enable 0x4X = Trigger Pulse/Trigger Enable Select 0x8X = Trigger Clear GEN 5 FIFO Trigger Control bit values: Register Value Trigger Type Trigger Edge --------------------------------------------------- 0x100 continuous positive 0x101 single sample positive 0x110 continuous negative 0x111 single sample negative 0x120 continuous positive 0x121 single sample positive or negative 0x130 continuous Software Trigger. 0x131 single sample Software Trigger 0x0XX Disable Trigger (will stop FIFO from storing data if continuously running) Trigger Configuration Format: (LSB) B0-B1 = Trigger Type 0xXX0 = Continuous 0xXX1 = Single Sample B2 = Don't care B3 = Don't care B4-B5 = Trigger Edge 0xX0X = Positive Edge 0xX1X = Negative Edge 0xX2X = Either Edge 0xX3X = Software Trigger (MSB) B8 = Trigger Enable 0x0XX = Not Enabled / Stop Trigger 0x1XX = Enable Trigger
cardIndex | : (Input) Logical Card Index assigned to connection with the NAI_BOARD (0 - NAI_MAX_CARDS-1). |
module | : (Input) Module Number of the module to access (1 - [max modules for board]). |
channel | : (Input) (Ignored in GEN5) Channel Number of the channel to access (1 - [max channels for module]). |
p_outctrl | : (Output) FIFO Trigger Control. |
NAIBRDFUNC nai_status_t NAIAPI naibrd_AD_ReadFIFO | ( | int32_t | cardIndex, |
int32_t | module, | ||
int32_t | channel, | ||
uint32_t | count, | ||
float64_t | p_outdata[], | ||
uint32_t * | p_outread ) |
Retrieves data elements from the A/D channel's FIFO buffer. The data is retrieved in two's complement format, and is then converted into floating-point format. If floating-point mode is enabled for the module, the data will be converted into IEEE 754 (32-bit) floating-point format. If floating-point mode is disabled, the data is converted into floating-point format based on the following specifications: For bipolar mode; 0x7FFF equals Positive Full Scale, 0x8000 equals Negative Full Scale. For unipolar mode, the range is from 0x0000 to 0xFFFF where 0xFFFF equals Full Scale. Full Scale is the maximum value of the range.
cardIndex | : (Input) Logical Card Index assigned to connection with the NAI_BOARD (0 - NAI_MAX_CARDS-1). |
module | : (Input) Module Number of the module to access (1 - [max modules for board]). |
channel | : (Input) Channel Number of the channel to access (1 - [max channels for module]). |
count | : (Input) Number of data elements to retrieve. |
p_outdata[] | : (Output) Array of 64-bit floating-point data. |
p_outread | :(Output) Number of data elements read from the A/D channel's FIFO buffer. |
NAIBRDFUNC nai_status_t NAIAPI naibrd_AD_ReadFIFORaw32 | ( | int32_t | cardIndex, |
int32_t | module, | ||
int32_t | channel, | ||
uint32_t | count, | ||
uint32_t | p_outdata[], | ||
uint32_t * | p_outread ) |
Retrieves data elements from the A/D channel's FIFO buffer. The data is presented in two's complement format. For bipolar mode; 0x7FFF equals Positive Full Scale, 0x8000 equals Negative Full Scale. For unipolar mode, the range is from 0x0000 to 0xFFFF where 0xFFFF equals Full Scale.
cardIndex | : (Input) Logical Card Index assigned to connection with the NAI_BOARD (0 - NAI_MAX_CARDS-1). |
module | : (Input) Module Number of the module to access (1 - [max modules for board]). |
channel | : (Input) Channel Number of the channel to access (1 - [max channels for module]). |
count | : (Input) Number of data elements to retrieve. |
p_outdata[] | : (Output) Array of 16-bit raw data. |
p_outread | :(Output) Number of data elements read from the A/D channel's FIFO buffer. |
NAIBRDFUNC nai_status_t NAIAPI naibrd_AD_SetFIFOAlmostEmpty | ( | int32_t | cardIndex, |
int32_t | module, | ||
int32_t | channel, | ||
uint32_t | empty ) |
Sets the almost empty mark to use to set or reset the A/D channel's FIFO Status "Almost Empty" bit. When the A/D channel's FIFO counter is less than or equal to the almost empty mark, the "Almost Empty" bit will be set. When the A/D channel's FIFO counter is greater than the almost empty mark, the "Almost Empty" bit will be reset.
cardIndex | : (Input) Logical Card Index assigned to connection with the NAI_BOARD (0 - NAI_MAX_CARDS-1). |
module | : (Input) Module Number of the module to access (1 - [max modules for board]). |
channel | : (Input) Channel Number of the channel to access (1 - [max channels for module]). |
empty | : (Input) Almost Empty Mark (module specific range- see spec). |
NAIBRDFUNC nai_status_t NAIAPI naibrd_AD_SetFIFOAlmostFull | ( | int32_t | cardIndex, |
int32_t | module, | ||
int32_t | channel, | ||
uint32_t | full ) |
Sets the almost full mark to use to set or reset the A/D channel's FIFO Status "Almost Full" bit. When the A/D channel's FIFO counter is less than or equal to the almost full mark, the "Almost Full" bit will be set. When the A/D channel's FIFO counter is greater than the almost full mark, the "Almost Full" bit will be reset.
cardIndex | : (Input) Logical Card Index assigned to connection with the NAI_BOARD (0 - NAI_MAX_CARDS-1). |
module | : (Input) Module Number of the module to access (1 - [max modules for board]). |
channel | : (Input) Channel Number of the channel to access (1 - [max channels for module]). |
full | : (Input) Almost Full Mark. (module specific range- see spec). |
NAIBRDFUNC nai_status_t NAIAPI naibrd_AD_SetFIFOCtrl | ( | int32_t | cardIndex, |
int32_t | module, | ||
int32_t | channel, | ||
naibrd_ad_fifo_ctrl_t | ctrl ) |
Sets the format of the samples to be stored in the A/D channel's FIFO buffer.
GEN3 Bit Format: (LSB) B0 - Data (16-bit High) 16-bit resolution data for unipolar and bipolar A/D data. B1 - Data (8-bit Low) Combined with B0 to form a 24-bit resolution data for unipolar and bipolar A/D data. B2 - Data Type (0 = Raw (unfiltered), 1 = Filtered). B3 - Reserved B4 - Time Stamp An integer counter that counts from 0 to 65,535 and wraps when it overflows. B5 - Reserved B6 - Reserved (MSB) B7 - Reserved Each data format (B0 - B4) requires one data element of storage space from the FIFO buffer. If B0, B1 and B4 are set (0x13), 3 data elements will be written to the FIFO per sample. GEN5 Bit Format: (LSB) B0 - Reserved B1 - Reserved B2 - Data Type (0 = Raw (unfiltered), 1 = Filtered). B3 - Reserved B4 - Time Stamp An integer counter that counts from 0 to 65,535 and wraps when it overflows. B5 - Reserved B6 - Reserved (MSB) B7 - Reserved Sample data requires element of storage space from the FIFO buffer. If B4 is set (0x1X), 2 data elements will be written to the FIFO per sample (1 element is data and 1 element is the timeStamp).
Note, the Fifo Size register should be adjusted to account for the number of data elements placed on the FIFO per sample to prevent an overflow of the FIFO buffer. For eample, if the Fifo Size is set to 1, and the Buffer Control B4 bit is set, an overflow condition will occur after the first sample. When an overflow condition occurs, any un-stored data will be lost. The values in Fifo Size and Buffer Control registers should be set to avoid an overflow of the FIFO buffer.
cardIndex | : (Input) Logical Card Index assigned to connection with the NAI_BOARD (0 - NAI_MAX_CARDS-1). |
module | : (Input) Module Number of the module to access (1 - [max modules for board]). |
channel | : (Input) Channel Number of the channel to access (1 - [max channels for module]). |
ctrl | : (Input) FIFO Data Sample Format. |
NAIBRDFUNC nai_status_t NAIAPI naibrd_AD_SetFIFODelay | ( | int32_t | cardIndex, |
int32_t | module, | ||
int32_t | channel, | ||
uint32_t | delay ) |
Sets the number of delay samples before the actual FIFO data collection begins. The data collected during the delay period will be discarded.
cardIndex | : (Input) Logical Card Index assigned to connection with the NAI_BOARD (0 - NAI_MAX_CARDS-1). |
module | : (Input) Module Number of the module to access (1 - [max modules for board]). |
channel | : (Input) Channel Number of the channel to access (1 - [max channels for module]). |
delay | : (Input) Number of delay samples before FIFO data collection (0 - 65535 (0xFFFF)). |
NAIBRDFUNC nai_status_t NAIAPI naibrd_AD_SetFIFOHiThreshold | ( | int32_t | cardIndex, |
int32_t | module, | ||
int32_t | channel, | ||
uint32_t | threshold ) |
Sets the high threshold level to use to set or reset the A/D channel's FIFO Status "High Limit" bit. When the A/D channel's FIFO counter is greater than or equal to the high threshold level, the "High Limit" bit will be set. When the A/D channel's FIFO counter is less than the high threshold level, the "High Limit" bit will be reset.
cardIndex | : (Input) Logical Card Index assigned to connection with the NAI_BOARD (0 - NAI_MAX_CARDS-1). |
module | : (Input) Module Number of the module to access (1 - [max modules for board]). |
channel | : (Input) Channel Number of the channel to access (1 - [max channels for module]). |
threshold | : (Input) High Threshold Level. (0 - 26,213 (0x6665)). |
NAIBRDFUNC nai_status_t NAIAPI naibrd_AD_SetFIFOLoThreshold | ( | int32_t | cardIndex, |
int32_t | module, | ||
int32_t | channel, | ||
uint32_t | threshold ) |
Sets the low threshold level to use to set or reset the A/D channel's FIFO Status "Low Limit" bit. When the A/D channel's FIFO counter is less than or equal to the low threshold level, the "Low Limit" bit will be set. When the A/D channel's FIFO counter is greater than the low threshold level, the "Low Limit" bit will be reset.
cardIndex | : (Input) Logical Card Index assigned to connection with the NAI_BOARD (0 - NAI_MAX_CARDS-1). |
module | : (Input) Module Number of the module to access (1 - [max modules for board]). |
channel | : (Input) Channel Number of the channel to access (1 - [max channels for module]). |
threshold | : (Input) Low Threshold Level. (0 - 26,213 (0x6665)). |
NAIBRDFUNC nai_status_t NAIAPI naibrd_AD_SetFIFOSize | ( | int32_t | cardIndex, |
int32_t | module, | ||
int32_t | channel, | ||
uint32_t | size ) |
Sets the number of samples to be taken and placed into the FIFO before the A/D channel's FIFO Status "Sample Done" bit is set after a trigger occurs. Note that the size of each sample (number of words written to the FIFO per sample) is determined by the sample format described by the Buffer Control register.
cardIndex | : (Input) Logical Card Index assigned to connection with the NAI_BOARD (0 - NAI_MAX_CARDS-1). |
module | : (Input) Module Number of the module to access (1 - [max modules for board]). |
channel | : (Input) Channel Number of the channel to access (1 - [max channels for module]). |
size | : (Input) Number of samples before FIFO trigger (0 - 65535 (0xFFFF)). |
NAIBRDFUNC nai_status_t NAIAPI naibrd_AD_SetFIFOSkip | ( | int32_t | cardIndex, |
int32_t | module, | ||
int32_t | channel, | ||
uint32_t | skip ) |
Sets the skip count for the FIFO buffer. The FIFO skip count sets how many samples to skip over in between each FIFO store. For example, if the sample rate for a channel is 10kHz, there would be a new sample every 100 micro-seconds. By setting the FIFO skip count to 1, the FIFO would store a new sample every 200us, or in other words, at a 5kHz rate.
cardIndex | : (Input) Logical Card Index assigned to connection with the NAI_BOARD (0 - NAI_MAX_CARDS-1). |
module | : (Input) Module Number of the module to access (1 - [max modules for board]). |
channel | : (Input) Channel Number of the channel to access (1 - [max channels for module]). |
skip | : (Input) Skip count (0 - (0xFFFF FFFF) ). |
NAIBRDFUNC nai_status_t NAIAPI naibrd_AD_SetFIFOTrigCtrl | ( | int32_t | cardIndex, |
int32_t | module, | ||
int32_t | channel, | ||
naibrd_ad_fifo_trig_t | ctrl ) |
Sets the A/D channel's FIFO buffer trigger control configuration.
GEN 3 FIFO Trigger Control bit values: Register Value Trigger Source Slope --------------------------------------------------- 0x20 External Trigger 2 Positive 0x21 External Trigger 1 Positive 0x22 Software Trigger N/A 0x30 External Trigger 2 Negative 0x31 External Trigger 1 Negative 0x32 Software Trigger N/A 0x40 Initiate 0x80 Stop (Clear Trigger) Trigger Configuration Format: (LSB) B0-B1 = Source Select 0x0 = External Trigger 2 0x1 = External Trigger 1 0x2 = Software Trigger B3 = Reserved (MSB) B4-B7 = Trigger Type 0x1X = Negative Slope 0x2X = Trigger Pulse Enable 0x4X = Trigger Pulse/Trigger Enable Select 0x8X = Trigger Clear GEN 5 FIFO Trigger Control bit values: Register Value Trigger Type Trigger Edge --------------------------------------------------- 0x100 continuous positive 0x101 single sample positive 0x110 continuous negative 0x111 single sample negative 0x120 continuous positive 0x121 single sample positive or negative 0x130 continuous Software Trigger. 0x131 single sample Software Trigger 0x0XX Disable Trigger (will stop FIFO from storing data if continuously running) Trigger Configuration Format: (LSB) B0-B1 = Trigger Type 0xXX0 = Continuous 0xXX1 = Single Sample B2 = Don't care B3 = Don't care B4-B5 = Trigger Edge 0xX0X = Positive Edge 0xX1X = Negative Edge 0xX2X = Either Edge 0xX3X = Software Trigger (MSB) B8 = Trigger Enable 0x0XX = Not Enabled / Stop Trigger 0x1XX = Enable Trigger
cardIndex | : (Input) Logical Card Index assigned to connection with the NAI_BOARD (0 - NAI_MAX_CARDS-1). |
module | : (Input) Module Number of the module to access (1 - [max modules for board]). |
channel | : (Input) (Ignored in GEN5) Channel Number of the channel to access (1 - [max channels for module]). |
ctrl | : (Input) FIFO Trigger Control. |
NAIBRDFUNC nai_status_t NAIAPI naibrd_AD_SoftwareTrigger | ( | int32_t | cardIndex, |
int32_t | module ) |
Sets the A/D module's FIFO Buffer Software Trigger register to 1. The Software trigger is used to kick start the FIFO buffer and the collection of data. The Trigger Control Configuration for each A/D channel's FIFO must be set up properly before invoking this routine. Setting the Software Trigger will start FIFO data collection for all A/D channels.
cardIndex | : (Input) Logical Card Index assigned to connection with the NAI_BOARD (0 - NAI_MAX_CARDS-1). |
module | : (Input) Module Number of the module to access (1 - [max modules for board]). |