Software Library API naibrd 2.24.0
See all documentation at naii.docs.com
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Functions | |
NAIBRDFUNC naibrd_1553_t NAIAPI | naibrd_1553_SetIrqCfg (int16_t device, naibrd_1553_general_interruptMode_t interruptMode, naibrd_1553_general_autoClear_t autoClear) |
Sets the type of interrupt signal to be generated by the device. | |
NAIBRDFUNC naibrd_1553_t NAIAPI | naibrd_1553_SetIrqEnable (int16_t device, uint16_t enable, uint32_t irqMask, void(*p_externalIsr)(int16_t device, uint32_t irqStatus)) |
Enables the interrupt conditions specified by the interrupt mask. NOTE: This function is not supported for FTJ/FTK modules. Please use naibrd_1760_SetIrqManipulate instead. | |
NAIBRDFUNC naibrd_1553_t NAIAPI | naibrd_1553_SetInterruptSteering (int16_t device, naibrd_int_steering_t steering) |
Sets the Interrupt Steering which indicates the interrupt direction for the 1553 device. | |
NAIBRDFUNC naibrd_1553_t NAIAPI | naibrd_1553_SetIntVector (int16_t device, int32_t intVector) |
Set the interrupt vector of the 1553 device.The vector value uniquely identifies the source of the interrupt in case multiple (1553 and/or non-1553) devices/channels are generating interrupts. | |
NAIBRDFUNC naibrd_1553_t NAIAPI | naibrd_1553_GetIntStatus (int16_t device, uint16_t *status1, uint16_t *status2) |
Reads the interrupt status registers #1 and #2. The status registers report any hardware events that have occurred. If the interrupt is enabled for a particular event, an interrupt will be generated when that event occurs. NOTE: This function is not supported for FTJ/FTK modules. Please use naibrd_1760_GetIntStatus instead. | |
NAIBRDFUNC naibrd_1553_t NAIAPI | naibrd_1553_ClearIntLatch (int16_t device) |
Clears the interrupt latch register. When an interrupt is generated by the core, bit 0 of the latch register is set high. This must be cleared by writing a '1' to the bit in order to receive more interrupts. | |
NAIBRDFUNC naibrd_1553_t NAIAPI naibrd_1553_ClearIntLatch | ( | int16_t | device | ) |
Clears the interrupt latch register. When an interrupt is generated by the core, bit 0 of the latch register is set high. This must be cleared by writing a '1' to the bit in order to receive more interrupts.
device | : (Input) Logical Device Number (0-31). |
NAIBRDFUNC naibrd_1553_t NAIAPI naibrd_1553_GetIntStatus | ( | int16_t | device, |
uint16_t * | status1, | ||
uint16_t * | status2 ) |
Reads the interrupt status registers #1 and #2. The status registers report any hardware events that have occurred. If the interrupt is enabled for a particular event, an interrupt will be generated when that event occurs. NOTE: This function is not supported for FTJ/FTK modules. Please use naibrd_1760_GetIntStatus instead.
device | : (Input) Logical Device Number (0-31). |
status1 | : (Output) Interrupt Status Register #1. This value will be an OR'ed combination of the following: NAIBRD_1553_INT_REG1_MASK_END_OF_MSG Bit 0. End of message (BC, RT and MT). NAIBRD_1553_INT_REG1_MASK_BC_STATUS_SET Bit 1. RT status received with incorrect RT address. NAIBRD_1553_INT_REG1_MASK_RT_MODE_CODE Bit 1. Mode code message received. NAIBRD_1553_INT_REG1_MASK_MT_PATTERN_TRIG Bit 1. Pattern Trigger interrupt if command word matches bit pattern in the Monitor Trigger Register. NAIBRD_1553_INT_REG1_MASK_FORMAT_ERROR Bit 2. Loop test failure or message error. NAIBRD_1553_INT_REG1_MASK_BC_END_OF_FRAME Bit 3. In non-enhanced BC mode, end of message frame. NAIBRD_1553_INT_REG1_MASK_BC_END_OF_MSG Bit 4. BC end of message. NAIBRD_1553_INT_REG1_MASK_RT_SUBADDR_END_OF_MSG Bit 4. RT subaddress end of message. NAIBRD_1553_INT_REG1_MASK_RT_CIRC_BUF_ROLLOVER Bit 5. RT circular buffer rollover. NAIBRD_1553_INT_REG1_MASK_TIME_TAG_ROLLOVER Bit 6. Time tag register rollover. NAIBRD_1553_INT_REG1_MASK_RT_ADDR_PARITY_ERROR Bit 7. RT address parity error. NAIBRD_1553_INT_REG1_MASK_BC_RETRY Bit 8. BC message retry. NAIBRD_1553_INT_REG1_MASK_HANDSHAKE_FAILURE Bit 9. Handshake timeout. NAIBRD_1553_INT_REG1_MASK_MT_DATA_STK_ROLLOVER Bit 10. Data stack rollover. NAIBRD_1553_INT_REG1_MASK_MT_CMD_STK_ROLLOVER Bit 11. MT command stack rollover. NAIBRD_1553_INT_REG1_MASK_BC_RT_CMD_STK_ROLLOVER Bit 12. BC/RT command stack rollover. NAIBRD_1553_INT_REG1_MASK_BC_RT_TX_TIMEOUT Bit 13. BC/RT Tx timeout. NAIBRD_1553_INT_REG1_MASK_RAM_PARITY_ERROR Bit 14. RAM parity error. NAIBRD_1553_INT_REG1_MASK_MASTER_INTERRUPT Bit 15. Master Interrupt (Indicates pending hardware interrupt). |
status2 | : (Output) Interrupt Status Register #2. This value will be an OR'ed combination of the following: NAIBRD_1553_INT_REG2_MASK_INTERRUPT_CHAIN Bit 0. Indicates Interrupt Register #1 is requesting interrupt. NAIBRD_1553_INT_REG2_MASK_BIT_COMPLETE Bit 1. Built in test complete. NAIBRD_1553_INT_REG2_MASK_BC_IRQ0 Bit 2. BC IRQ h/w instruction generated. NAIBRD_1553_INT_REG2_MASK_BC_IRQ1 Bit 3. BC IRQ h/w instruction generated. NAIBRD_1553_INT_REG2_MASK_BC_IRQ2 Bit 4. BC IRQ h/w instruction generated. NAIBRD_1553_INT_REG2_MASK_BC_IRQ3 Bit 5. BC IRQ h/w instruction generated. NAIBRD_1553_INT_REG2_MASK_MT_DATA_STK_HALF_ROLLOVER Bit 6. MT data stack 50% full. NAIBRD_1553_INT_REG2_MASK_MT_CMD_STK_HALF_ROLLOVER Bit 7. MT command stack 50% full. NAIBRD_1553_INT_REG2_MASK_RT_CIRC_BUF_HALF_ROLLOVER Bit 8. RT circular buffer rollover. NAIBRD_1553_INT_REG2_MASK_RT_CMD_STK_HALF_ROLLOVER Bit 9. RT command stack rollover. NAIBRD_1553_INT_REG2_MASK_BC_TRAP Bit 10. BC trap - illegal opcode or watchdog timeout. NAIBRD_1553_INT_REG2_MASK_BC_CALL_STK_ERROR Bit 11. BC call stack overflow/underflow error. NAIBRD_1553_INT_REG2_MASK_GPQ_ISQ_ROLLOVER Bit 12. BC GPQ rollover/RT ISQ rollover. NAIBRD_1553_INT_REG2_MASK_RT_ILLEGAL_COMMAND Bit 13. RT received illegal message. NAIBRD_1553_INT_REG2_MASK_BC_OPCODE_PARITY_ERROR Bit 14. BC instruction opcode parity error. NAIBRD_1553_INT_REG2_MASK_MASTER_INTERRUPT Bit 15. Master Interrupt (Indicates pending hardware interrupt). |
NAIBRDFUNC naibrd_1553_t NAIAPI naibrd_1553_SetInterruptSteering | ( | int16_t | device, |
naibrd_int_steering_t | steering ) |
Sets the Interrupt Steering which indicates the interrupt direction for the 1553 device.
device | : (Input) Logical Device Number (0-31). |
steering | : (Input) Interrupt Steering. Select from the following: NAIBRD_INT_STEERING_VME Direct interrupt to VME Bus NAIBRD_INT_STEERING_ON_BOARD_0 Direct interrupt to the Custom Application on ARM NAIBRD_INT_STEERING_ON_BOARD_1 Direct interrupt to the NAI Ethernet Listener Application NAIBRD_INT_STEERING_ON_BOARD_2 Currently not used NAIBRD_INT_STEERING_PCIE_APP Direct interrupt to PCIe Bus NAIBRD_INT_STEERING_CPCI_APP Direct interrupt to CPCI Bus |
NAIBRDFUNC naibrd_1553_t NAIAPI naibrd_1553_SetIntVector | ( | int16_t | device, |
int32_t | intVector ) |
Set the interrupt vector of the 1553 device.The vector value uniquely identifies the source of the interrupt in case multiple (1553 and/or non-1553) devices/channels are generating interrupts.
device | : (Input) Logical Device Number (0-31). |
intVector | : (Input) Interrupt vector. |
NAIBRDFUNC naibrd_1553_t NAIAPI naibrd_1553_SetIrqCfg | ( | int16_t | device, |
naibrd_1553_general_interruptMode_t | interruptMode, | ||
naibrd_1553_general_autoClear_t | autoClear ) |
Sets the type of interrupt signal to be generated by the device.
device | : (Input) Logical Device Number (0-31). |
interruptMode | : (Input) Interrupt Operation Mode Select (NAIBRD_1553_IRQ_MODE_LEVEL, NAIBRD_1553_IRQ_MODE_PULSE). |
autoClear | : (Input) Register Read and Clear Operation Mode Select (NAIBRD_1553_IRQ_AUTO_CLEAR, NAIBRD_1553_IRQ_NO_AUTO_CLEAR). |
NAIBRDFUNC naibrd_1553_t NAIAPI naibrd_1553_SetIrqEnable | ( | int16_t | device, |
uint16_t | enable, | ||
uint32_t | irqMask, | ||
void(* | p_externalIsr )(int16_t device, uint32_t irqStatus) ) |
Enables the interrupt conditions specified by the interrupt mask. NOTE: This function is not supported for FTJ/FTK modules. Please use naibrd_1760_SetIrqManipulate instead.
device | : (Input) Logical Device Number (0-31). |
enable | : (Input) Enable (1) or disable (0) interrupts. |
irqMask | : (Input) Bit mask to set the desired interrupt bits in the interrupt registers. The following bit masks, which correspond to a bit in the interrupt registers 1 and 2, may be logically OR'ed together to enable or disable multiple interrupt conditions. NAIBRD_1553_INT_REG1_MASK_END_OF_MSG End of message (BC, RT and MT). NAIBRD_1553_INT_REG1_MASK_BC_STATUS_SET RT status received with incorrect RT address. NAIBRD_1553_INT_REG1_MASK_RT_MODE_CODE Mode code message received. NAIBRD_1553_INT_REG1_MASK_MT_PATTERN_TRIG Pattern Trigger interrupt if command word matches bit pattern in the Monitor Trigger Register. NAIBRD_1553_INT_REG1_MASK_FORMAT_ERROR Loop test failure or message error. NAIBRD_1553_INT_REG1_MASK_BC_END_OF_FRAME In non-enhanced BC mode, end of message frame. NAIBRD_1553_INT_REG1_MASK_BC_END_OF_MSG BC end of message. NAIBRD_1553_INT_REG1_MASK_RT_SUBADDR_END_OF_MSG RT subaddress end of message. NAIBRD_1553_INT_REG1_MASK_RT_CIRC_BUF_ROLLOVER RT circular buffer rollover. NAIBRD_1553_INT_REG1_MASK_TIME_TAG_ROLLOVER Time tag register rollover. NAIBRD_1553_INT_REG1_MASK_RT_ADDR_PARITY_ERROR RT address parity error. NAIBRD_1553_INT_REG1_MASK_BC_RETRY BC message retry. NAIBRD_1553_INT_REG1_MASK_HANDSHAKE_FAILURE Handshake timeout. NAIBRD_1553_INT_REG1_MASK_MT_DATA_STK_ROLLOVER Data stack rollover. NAIBRD_1553_INT_REG1_MASK_MT_CMD_STK_ROLLOVER MT command stack rollover. NAIBRD_1553_INT_REG1_MASK_BC_RT_CMD_STK_ROLLOVER BC/RT command stack rollover. NAIBRD_1553_INT_REG1_MASK_BC_RT_TX_TIMEOUT BC/RT Tx timeout. NAIBRD_1553_INT_REG1_MASK_RAM_PARITY_ERROR RAM parity error. NAIBRD_1553_INT_REG2_MASK_BIT_COMPLETE Built in test complete. NAIBRD_1553_INT_REG2_MASK_BC_IRQ0 BC IRQ h/w instruction generated. NAIBRD_1553_INT_REG2_MASK_BC_IRQ1 BC IRQ h/w instruction generated. NAIBRD_1553_INT_REG2_MASK_BC_IRQ2 BC IRQ h/w instruction generated. NAIBRD_1553_INT_REG2_MASK_BC_IRQ3 BC IRQ h/w instruction generated. NAIBRD_1553_INT_REG2_MASK_MT_DATA_STK_HALF_ROLLOVER MT data stack 50% full. NAIBRD_1553_INT_REG2_MASK_MT_CMD_STK_HALF_ROLLOVER MT command stack 50% full. NAIBRD_1553_INT_REG2_MASK_RT_CIRC_BUF_HALF_ROLLOVER RT circular buffer rollover. NAIBRD_1553_INT_REG2_MASK_RT_CMD_STK_HALF_ROLLOVER RT command stack rollover. NAIBRD_1553_INT_REG2_MASK_BC_TRAP BC trap - illegal opcode or watchdog timeout. NAIBRD_1553_INT_REG2_MASK_BC_CALL_STK_ERROR BC call stack overflow/underflow error. NAIBRD_1553_INT_REG2_MASK_GPQ_ISQ_ROLLOVER BC GPQ rollover/RT ISQ rollover. NAIBRD_1553_INT_REG2_MASK_RT_ILLEGAL_CMD RT received illegal message. NAIBRD_1553_INT_REG2_MASK_BC_OPCODE_PARITY_ERROR BC instruction opcode parity error. |
p_externalIsr | : (Input) This is unused. NULL is a valid value. |