Functions
NAIBRDFUNC naibrd_1760_t NAIAPI	naibrd_1760_SetIrqManipulate (int16_t swDevice, uint16_t bIsInterruptEnabled, uint16_t wHardwareIrqMask, uint16_t wBcIrqMask, uint16_t wRtIrqMask, uint16_t wMtIrqMask, void(funcpExternalIsr)(void param, uint32_t vector))
	Enables the interrupt conditions specified by the interrupt mask. NOTE: This function is only supported for FTJ/FTK modules. Please use naibrd_1553_SetIrqManipulate for FT[1-9].

NAIBRDFUNC naibrd_1760_t NAIAPI	naibrd_1760_GetIntStatus (int16_t swDevice, uint16_t wHardwareStatus, uint16_t wBcStatus, uint16_t wRtStatus, uint16_t wMtStatus)
	Reads the interrupt status pending registers. NOTE: This function is only supported for FTJ/FTK modules. Please use naibrd_1553_GetIntStatus for FT[1-9].

Detailed Description

Function Documentation

◆ naibrd_1760_GetIntStatus()

NAIBRDFUNC naibrd_1760_t NAIAPI naibrd_1760_GetIntStatus	(	int16_t	swDevice,
		uint16_t *	wHardwareStatus,
		uint16_t *	wBcStatus,
		uint16_t *	wRtStatus,
		uint16_t *	wMtStatus )

Reads the interrupt status pending registers. NOTE: This function is only supported for FTJ/FTK modules. Please use naibrd_1553_GetIntStatus for FT[1-9].

Parameters

swDevice	: (Input) Logical Device Number (0-31).
wHardwareStatus	: (Output) Bit mask to set the desired interrupt bits in the hardware interrupt enable register. The following bit masks, which correspond to a bit in the hardware interrupt enable register, may be logically OR'ed together to enable or disable multiple interrupt conditions. NAIBRD_1760_HARDWARE_INTERRUPT_MASK_HSPIINT Bit 15. Host SPI Interrupt NAIBRD_1760_HARDWARE_INTERRUPT_MASK_EECKE Bit 14. EEPROM Checksum Error Interrupt NAIBRD_1760_HARDWARE_INTERRUPT_MASK_UNCRE Bit 14. Uncorrected 24K RAM Error Interrupt NAIBRD_1760_HARDWARE_INTERRUPT_MASK_RAMIF Bit 13. RAM Initialization Fail Interrupt NAIBRD_1760_HARDWARE_INTERRUPT_MASK_RAMERR Bit 13. Detected and Corrected 24K RAM Error Interrupt NAIBRD_1760_HARDWARE_INTERRUPT_MASK_LBFA Bit 12. Loopback Fail Bus A Interrupt (RT only) NAIBRD_1760_HARDWARE_INTERRUPT_MASK_LBFB Bit 11. Loopback Fail Bus B Interrupt (RT only) NAIBRD_1760_HARDWARE_INTERRUPT_MASK_MTTTRO Bit 10. MT Time Tag Counter Interrupt NAIBRD_1760_HARDWARE_INTERRUPT_MASK_BCTTRO Bit 9. BC Time Tag Counter Interrupt NAIBRD_1760_HARDWARE_INTERRUPT_MASK_RT2TTM Bit 8. RT2 Time Tag Match Interrupt NAIBRD_1760_HARDWARE_INTERRUPT_MASK_RT1TTM Bit 7. RT1 Time Tag Match Interrupt NAIBRD_1760_HARDWARE_INTERRUPT_MASK_MTTTM Bit 6. MT Time Tag Match Interrupt NAIBRD_1760_HARDWARE_INTERRUPT_MASK_BCTTM Bit 5. BC Time Tag Match Interrupt NAIBRD_1760_HARDWARE_INTERRUPT_MASK_RT2APF Bit 4. RT2 Terminal Address Parity Fail Interrupt NAIBRD_1760_HARDWARE_INTERRUPT_MASK_RT1APF Bit 3. RT1 Terminal Address Parity Fail Interrupt NAIBRD_1760_HARDWARE_INTERRUPT_MASK_RTIP Bit 2. RT Interrupt Pending NAIBRD_1760_HARDWARE_INTERRUPT_MASK_MTIP Bit 1. MT Interrupt Pending NAIBRD_1760_HARDWARE_INTERRUPT_MASK_BCIP Bit 0. BC Interrupt Pending
wBcStatus	: (Output) Bit mask to set the desired interrupt bits in the BC interrupt enable register. The following bit masks, which correspond to a bit in the BC interrupt enable register, may be logically OR'ed together to enable or disable multiple interrupt conditions. NAIBRD_1760_BC_INTERRUPT_MASK_BCWDT Bit 15. BC Watchdog Timer Interrupt NAIBRD_1760_BC_INTERRUPT_MASK_SELMSG Bit 14. BC Selected Message Interrupt NAIBRD_1760_BC_INTERRUPT_MASK_BCGPQ Bit 13. BC General Purpose Queue Rollover Interrupt NAIBRD_1760_BC_INTERRUPT_MASK_BCRETRY Bit 12. BC Retry Interrupt NAIBRD_1760_BC_INTERRUPT_MASK_CSTKERR Bit 11. BC Call Stack Pointer Error Interrupt NAIBRD_1760_BC_INTERRUPT_MASK_BCTRAP Bit 10. Trap Interrupt NAIBRD_1760_BC_INTERRUPT_MASK_STATSET Bit 9. Status Set Interrupt NAIBRD_1760_BC_INTERRUPT_MASK_BCIRQ Bits 8 to 5. Interrupt Request Bits 3-0 NAIBRD_1760_BC_INTERRUPT_MASK_BCMERR Bit 4. Message Error Interrupt NAIBRD_1760_BC_INTERRUPT_MASK_BCEOM Bit 3. End of Message Interrupt
wRtStatus	: (Output) Bit mask to set the desired interrupt bits in the RT interrupt enable register. The following bit masks, which correspond to a bit in the RT interrupt enable register, may be logically OR'ed together to enable or disable multiple interrupt conditions. NAIBRD_1760_RT_INTERRUPT_MASK_RT2MC8 Bit 15. RT 2 Mode Code 8 Command Interrupt NAIBRD_1760_RT_INTERRUPT_MASK_IXEQZ2 Bit 14. RT 2 Index Equals Zero Interrupt NAIBRD_1760_RT_INTERRUPT_MASK_ILCMD2 Bit 13. RT 2 Illegal Command Interrupt NAIBRD_1760_RT_INTERRUPT_MASK_IBR2 Bit 12. RT 2 Broadcast Command Received Interrupt NAIBRD_1760_RT_INTERRUPT_MASK_MERR2 Bit 11. RT 2 Message Error Status Interrupt NAIBRD_1760_RT_INTERRUPT_MASK_IWA2 Bit 10. RT 2 Interrupt When Accessed NAIBRD_1760_RT_INTERRUPT_MASK_RT1MC8 Bit 8. RT 1 Mode Code 8 Command Interrupt NAIBRD_1760_RT_INTERRUPT_MASK_IXEQZ1 Bit 7. RT 1 Index Equals Zero Interrupt NAIBRD_1760_RT_INTERRUPT_MASK_ILCMD1 Bit 6. RT 1 Illegal Command Interrupt NAIBRD_1760_RT_INTERRUPT_MASK_IBR1 Bit 5. RT 1 Broadcast Command Received Interrupt NAIBRD_1760_RT_INTERRUPT_MASK_MERR1 Bit 4. RT 1 Message Error Status Interrupt NAIBRD_1760_RT_INTERRUPT_MASK_IWA1 Bit 3. RT 1 Interrupt When Accessed
wMtStatus	: (Output) Bit mask to set the desired interrupt bits in the MT interrupt enable register. The following bit masks, which correspond to a bit in the MT interrupt enable register, may be logically OR'ed together to enable or disable multiple interrupt conditions. NAIBRD_1760_MT_INTERRUPT_MASK_CBUFRO Bit 8. Command Buffer Rollover Interrupt NAIBRD_1760_MT_INTERRUPT_MASK_DBUFRO Bit 7. Data Buffer Rollover Interrupt NAIBRD_1760_MT_INTERRUPT_MASK_CBUFMAT Bit 6. Command Buffer Address Match Interrupt NAIBRD_1760_MT_INTERRUPT_MASK_DBUFMAT Bit 5. Data Buffer Address Match Interrupt NAIBRD_1760_MT_INTERRUPT_MASK_SMTMERR Bit 4. SMT Message Error Interrupt NAIBRD_1760_MT_INTERRUPT_MASK_SMTEOM Bit 3. SMT End of Message Interrupt

Returns

NAI_SUCCESS
NAI_1553_RC_INVALID_DEVICE_NUMBER when incorrect device number was input
NAI_ERROR_NOT_SUPPORTED when the function is not supported.

◆ naibrd_1760_SetIrqManipulate()

NAIBRDFUNC naibrd_1760_t NAIAPI naibrd_1760_SetIrqManipulate	(	int16_t	swDevice,
		uint16_t	bIsInterruptEnabled,
		uint16_t	wHardwareIrqMask,
		uint16_t	wBcIrqMask,
		uint16_t	wRtIrqMask,
		uint16_t	wMtIrqMask,
		void(*	funcpExternalIsr )(void *param, uint32_t vector) )

Enables the interrupt conditions specified by the interrupt mask. NOTE: This function is only supported for FTJ/FTK modules. Please use naibrd_1553_SetIrqManipulate for FT[1-9].