The purpose of the M1553_BC_Interrupt is to illustrate the methods to call in the naibrd library to configure the 1553 channel as a Bus Controller and to send various messages at different periodic rates. Specifically, Message 1 is sent at a rate of 4 Hz (every 250 ms), Message 2 is sent at a rate of 2 Hz (every 500 ms) and Message 3 is sent at a rate of 1 Hz (every 1000 ms). Three 250 ms minor frames are used to manage the periodicity of these messages. Minor Frame 1 contains Messages 1, 2 and 3. Minor Frame 2 contains Messages 1 and 2 only. Minor Frame 3 only contains Message 1. By chaining these frames together in the following order:
Minor Frame 1 | Minor Frame 3 | Minor Frame 2 | Minor Frame 3
Message 1 is sent every 250 ms, Message 2 is sent every 500 ms and Message 3 is sent every 1000 ms.
This application also demonstrates configuration and utilization of interrupts to signal the host processor whenever a 1553 message is sent out. The interrupt service callback routine sets a global flag to indicate a BC Rx Avail FIFO Status interrupt has been generated by the BC channel. When this occurs, the while loop in the main thread retrieves the FIFO data based on the fifo count. (NOTE: interrupt steering should be set in accordance with the onboard processor type, where steering is set to NAIBRD_INT_STEERING_PCIE for PPC1 and NAIBRD_INT_STEERING_ONBOARD_ARM for ARM1). Ethernet communication will not work with this application.
The following routines are called to configure and enable interrupts on the 1553 and hook the interrupt service routine (ISR).
- naibrd_InstallISR
- naibrd_1553_SetInterruptSteering
- naibrd_1553_SetMsgFIFOInterruptEnable
- naibrd_1553_SetMsgFIFOInterruptEdgeLevel
- naibrd_1553_SetIntVector
The following system configuration routines from the nai_sys_cfg.c file are called to assist with the configuration setup for this program prior to calling the naibrd 1553 routines.
- ConfigDevice
- DisplayDeviceCfg
- GetBoardSNModCfg
- CheckModule
1.11.0