Functions
static int32_t	GetChannelCount (uint32_t modid)

static int32_t	GetGroupCount (uint32_t modid)

static int32_t	GetGroupSize (uint32_t modid)

static nai_status_t	GetFIFOInfo (int32_t cardIndex, int32_t module, int32_t channel, uint32_t modid, uint32_t outcount, naibrd_dif_fifo_status_t outstatus)

static nai_status_t	naibrd_DIF_verify_channel (uint32_t modid, int32_t channel)

static nai_status_t	naibrd_DIF_verify_burstnum (int32_t burstnum)

static nai_status_t	naibrd_DIF_verify_timebase_values (uint32_t modid, float64_t time)

static nai_status_t	naibrd_DIF_verify_chan_mapped_status_type (naibrd_dif_chan_mapped_status_type_t type)

static nai_status_t	naibrd_DIF_verify_reset_type (naibrd_dif_reset_type_t type)

static nai_status_t	naibrd_DIF_verify_debounce_idx_type (int32_t modid, naibrd_dif_debounce_idx_t type)

static nai_status_t	naibrd_DIF_verify_enhaced_mode_type (naibrd_dif_enhanced_mode_t mode)

static nai_status_t	naibrd_DIF_verify_enable_type (naibrd_dif_enable_t type)

static nai_status_t	naibrd_DIF_verify_pwm_polarity_type (naibrd_dif_pwm_polarity_t type)

static nai_status_t	naibrd_DIF_verify_pattern_control_type (naibrd_dif_pattern_ctrl_t type)

static nai_status_t	naibrd_DIF_verify_pattern_length_type (int32_t dataPatternLen)

static nai_status_t	naibrd_DIF_verify_raw_module_type (naibrd_dif_raw_module_t type)

static nai_status_t	naibrd_DIF_verify_raw_channel_type (naibrd_dif_raw_channel_t type)

NAIBRDFUNC int32_t NAIAPI	naibrd_DIF_GetChannelCount (uint32_t modid)
	Returns the number of channels for the specified DIF Module ID.

NAIBRDFUNC int32_t NAIAPI	naibrd_DIF_GetGroupCount (uint32_t modid)
	Returns the number of channel groups for the specified DIF Module ID.

NAIBRDFUNC int32_t NAIAPI	naibrd_DIF_GetGroupSize (uint32_t modid)
	Returns the number of channel in each group for the specified DIF Module ID.

NAIBRDFUNC float64_t NAIAPI	naibrd_DIF_GetTimebaseLSB (uint32_t modid)
	Returns the LSB for the timer interval for Debounce, Measurement, PWM and Pattern Generator clocks for the specified DIF Module ID.

NAIBRDFUNC uint32_t NAIAPI	naibrd_DIF_GetValidPatternGenStart (uint32_t modid)
	Returns valid start address for Pattern RAM Generator block for the specified DIF Module ID.

NAIBRDFUNC uint32_t NAIAPI	naibrd_DIF_GetValidPatternGenEnd (uint32_t modid)
	Returns valid end address for Pattern RAM Generator block for the specified DIF Module ID.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetOutputState (int32_t cardIndex, int32_t module, int32_t channel, naibrd_dif_state_t state)
	Sets the Output State for the specified DIF channel.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetOutputState (int32_t cardIndex, int32_t module, int32_t channel, naibrd_dif_state_t *outstate)
	Retrieves the Output State for the specified DIF channel.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetInputState (int32_t cardIndex, int32_t module, int32_t channel, naibrd_dif_state_t *outstate)
	Retrieves the Input State for the specified DIF channel.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetChanMappedStatus (int32_t cardIndex, int32_t module, int32_t channel, naibrd_dif_chan_mapped_status_type_t type, nai_status_bit_t *outstatusVal)
	Retrieves the status for the specified DF1 channel and status type.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_ClearChanMappedStatus (int32_t cardIndex, int32_t module, int32_t channel, naibrd_dif_chan_mapped_status_type_t type)
	Clears the latched status for the specified DIF channel and status type.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetIOFormat (int32_t cardIndex, int32_t module, int32_t channel, naibrd_dif_ioformat_t format)
	Sets the Input/Output configuration for the specified DIF channel. Default configuration for the channels is input.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetIOFormat (int32_t cardIndex, int32_t module, int32_t channel, naibrd_dif_ioformat_t *outformat)
	Retrieves the Input/Output configuration for the specified DIF channel. Default configuration for the channels is input.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetOpMode (int32_t cardIndex, int32_t module, int32_t channel, naibrd_dif_enhanced_mode_t mode)
	Sets the Operation mode for the specified DIF channel. Default power on configuration for the channels is Enhanced Input. Selection of one of the basic modes will switch to transceiver (basic) mode operation with no signal processing.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetOpMode (int32_t cardIndex, int32_t module, int32_t channel, naibrd_dif_enhanced_mode_t *outmode)
	Retrieves the Operation mode for the specified DIF channel. Retrieves either Basic/Transceiver modes or Enhanced modes, depending whether the Basic Transceiver mode is enabled.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetSlewRate (int32_t cardIndex, int32_t module, int32_t channel, naibrd_dif_slewRate_t rate)
	Sets the slew rate for the specified DIF channel.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetSlewRate (int32_t cardIndex, int32_t module, int32_t channel, naibrd_dif_slewRate_t *outrate)
	Retrieves the Output slewrate for the specified DIF channel.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetInputTermination (int32_t cardIndex, int32_t module, int32_t channel, naibrd_dif_input_term_t InputTermination)
	Sets input termination of 120 ohms or >12k ohms (unterminated) for specified DIF channel.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetInputTermination (int32_t cardIndex, int32_t module, int32_t channel, naibrd_dif_input_term_t *InputTermination)
	Retrieves the input termination configuration for specified DIF channel.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_Reset (int32_t cardIndex, int32_t module, int32_t channel, naibrd_dif_reset_type_t resetType)
	Resets the DIF channel as specified by the reset type.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_ResetAll (int32_t cardIndex, int32_t module, naibrd_dif_reset_type_t resetType)
	Resets all channels on the module as specified by the reset type.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetDebounceTime (int32_t cardIndex, int32_t module, int32_t channel, float64_t debounceTime)
	Sets the debounce time for the specified channel. Enter time in milliseconds. When a signal level is within a valid logic range and maintains that level for a period longer than the debounce time, the logic transition is validated. Signal pulse widths less than debounce time are filtered or ignored. Once valid, the transition status is set and the output logic changes state. Enter a value of 0 to disable debounce filtering. Debounce defaults to 0 upon power on or reset.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetDebounceTime (int32_t cardIndex, int32_t module, int32_t channel, float64_t *outdebounceTime)
	Retrieves the debounce time for the specified TTL channel, in units of milliseconds. When a signal level is within a valid logic range and maintains that level for a period longer than the debounce time, the logic transition is validated. Signal pulse widths less than debounce time are filtered or ignored. Once valid, the transition status is set and the output logic changes state. A value of 0 disables debounce filtering. Debounce defaults to 0 upon power on or reset.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetDebounceLSB (int32_t cardIndex, int32_t module, float64_t debounceLSBtime)
	Sets the debounce LSB time value (applies to all the channels on the module). This debounce LSB time value coupled with the value in the individual channel debounce time registers will determine the effective debounce time for each channel. Feature presently available only on the D8 DIF module; LSB is fixed on other modules.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetDebounceLSB (int32_t cardIndex, int32_t module, float64_t *outdebounceLSBtime)
	Retrieves the debounce LSB time value, applicable for all channels on the module. This value, multiplied by the value set in the individual channel debounce time register determines the effective debounce time for each channel. For the D8 module, this LSB unit is user configurable. Debounce LSB is fixed in other modules.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetChanMappedInterruptEnable (int32_t cardIndex, int32_t module, int32_t channel, naibrd_dif_chan_mapped_status_type_t type, bool_t enable)
	Sets the Interrupt Enable for the specified DIF channel and interrupt status type.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetChanMappedInterruptEnable (int32_t cardIndex, int32_t module, int32_t channel, naibrd_dif_chan_mapped_status_type_t type, bool_t *outenable)
	Retrieves the Interrupt Enable for the specified DIF channel and interrupt status type.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetChanMappedInterruptTriggerType (int32_t cardIndex, int32_t module, int32_t channel, naibrd_dif_chan_mapped_status_type_t type, naibrd_dif_interrupt_t interruptType)
	Sets the Interrupt Edge/Level property for the specified DIF channel and interrupt status type.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetChanMappedInterruptTriggerType (int32_t cardIndex, int32_t module, int32_t channel, naibrd_dif_chan_mapped_status_type_t type, naibrd_dif_interrupt_t *outinterruptType)
	Retrieves the Interrupt Edge/Level property for the specified DIF channel and interrupt status type.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetChanMappedInterruptVector (int32_t cardIndex, int32_t module, naibrd_dif_chan_mapped_status_type_t type, uint32_t vector)
	Sets the Interrupt Vector for the specified DIF channel and interrupt status type.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetChanMappedInterruptVector (int32_t cardIndex, int32_t module, naibrd_dif_chan_mapped_status_type_t type, uint32_t *outvector)
	Retrieves the Interrupt Vector for the specified DIF channel and interrupt status type.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetChanMappedInterruptSteering (int32_t cardIndex, int32_t module, naibrd_dif_chan_mapped_status_type_t type, naibrd_int_steering_t steering)
	Sets the Interrupt Steering which indicates the interrupt direction for the specified DIF group and interrupt status type.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetChanMappedInterruptSteering (int32_t cardIndex, int32_t module, naibrd_dif_chan_mapped_status_type_t type, naibrd_int_steering_t *outsteering)
	Retrieves the Interrupt Steering which indicates the interrupt direction for the specified DIF group and interrupt status type.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetBITInterval (int32_t cardIndex, int32_t module, uint32_t bitInterval)
	Sets the BIT Error Interval. The BIT Error Interval essentially filter BIT errors prior to an actual notification of a BIT Error (maybe advantageous in "noisy/unstable" application environments or for general filtering purposes). The BIT Error Interval mechanism uses an up/down counter such that accumulated successive fault detections are counted up and no fault detections are counted down. The BIT Error Interval essentially sets up a threshold requirement of "successive" fault events to accumulate before actual notification of the fault.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetBITInterval (int32_t cardIndex, int32_t module, uint32_t *outbitInterval)
	Retrieves the BIT Error Interval. The BIT Error Interval essentially filter BIT errors prior to an actual notification of a BIT Error (maybe advantageous in "noisy/unstable" application environments or for general filtering purposes). The BIT Error Interval mechanism uses an up/down counter such that accumulated successive fault detections are counted up and no fault detections are counted down. The BIT Error Interval essentially sets up a threshold requirement of "successive" fault events to accumulate before actual notification of the fault.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetEnhanceTriggerEnable (int32_t cardIndex, int32_t module, int32_t channel, naibrd_dif_enable_t enable)
	Sets enhanced operation to disabled or enabled for specified Discrete channel.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetEnhanceTriggerEnable (int32_t cardIndex, int32_t module, int32_t channel, naibrd_dif_enable_t *outenable)
	Retrieves the present enhance operation enable state for the specified Discrete channel. Power on default configuration for the channels is Enhanced Input.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetPWM_Polarity (int32_t cardIndex, int32_t module, int32_t channel, naibrd_dif_pwm_polarity_t polarity)
	Sets the polarity for the PWM output for the selected channel on the module. Options are positive and negative polarity, where positive indicates the high state corresponds to the pulsewidth setting, and negative inverts it for a negative going pulse output.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetPWM_Polarity (int32_t cardIndex, int32_t module, int32_t channel, naibrd_dif_pwm_polarity_t *outpolarity)
	Retrieves the polarity setting for the PWM output for the selected channel on the module. Options are positive and negative polarity, where positive setting indicates the high state corresponds to the pulsewidth setting, and negative setting inverts it for a negative going pulse output.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetPWM_Pulsewidth (int32_t cardIndex, int32_t module, int32_t channel, float64_t pulsewidth)
	Sets the PWM pulsewidth for the specified DIF channel.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetPWM_Pulsewidth (int32_t cardIndex, int32_t module, int32_t channel, float64_t *outpulsewidth)
	Retrieves the PWM pulsewidth value set for the specified DIF channel.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetPWM_Period (int32_t cardIndex, int32_t module, int32_t channel, float64_t period)
	Sets the PWM period for the specified DIF channel.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetPWM_Period (int32_t cardIndex, int32_t module, int32_t channel, float64_t *outperiod)
	Retrieves the PWM period value set for the specified DIF channel.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetPWM_BurstNum (int32_t cardIndex, int32_t module, int32_t channel, uint32_t burstNum)
	Sets the number of cycles to output in the PWM burst mode for the specified DIF channel. The set value is applicable for enhanced IO PWM burst mode (mode 12).

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetPWM_BurstNum (int32_t cardIndex, int32_t module, int32_t channel, uint32_t *outburstNum)
	Retrieves the number of cycles set to output in the PWM burst mode for the specified DIF channel.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_StartPWM (int32_t cardIndex, int32_t module, int32_t channel)
	Starts the PWM output for the selected channel on the module.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_StopPWM (int32_t cardIndex, int32_t module, int32_t channel)
	Stops the PWM output for the selected channel on the module. For Gen5 modules, this is done by disabling the "Enhance Trigger Enable" register.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetPatternGenStartAddr (int32_t cardIndex, int32_t module, uint32_t startAddr)
	Sets the starting address to look at for RAM Pattern Generator.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetPatternGenStartAddr (int32_t cardIndex, int32_t module, uint32_t *outstartAddr)
	Gets the starting address to look at for RAM Pattern Generator.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetPatternGenEndAddr (int32_t cardIndex, int32_t module, uint32_t EndAddr)
	Sets the Ending address to look at for RAM Pattern Generator.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetPatternGenEndAddr (int32_t cardIndex, int32_t module, uint32_t *outEndAddr)
	Gets the Ending address to look at for RAM Pattern Generator.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetPatternGenPeriod (int32_t cardIndex, int32_t module, float64_t period_mS)
	Sets the period for the Pattern Generator for the specified Discrete channel.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetPatternGenPeriod (int32_t cardIndex, int32_t module, float64_t *outperiod_mS)
	Retrieves the period for the Pattern Generator for the specified Discrete channel.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetPatternGen_BurstNum (int32_t cardIndex, int32_t module, uint32_t burstNum)
	Sets the number of cycles to output in the PatternGen burst mode for the specified Discrete module. The set value is applicable for enhanced IO PatternGen burst mode.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetPatternGen_BurstNum (int32_t cardIndex, int32_t module, uint32_t *outburstNum)
	Retrieves the number of cycles set to output in the PatternGen burst mode for the specified Discrete module.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetPatternGenCtrl (int32_t cardIndex, int32_t module, naibrd_dif_pattern_ctrl_t controlBit, naibrd_dif_enable_t state)
	Sets the state for the RAM Pattern Generator for the selected control bit on the module. Options are enable and disable.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetPatternGenCtrl (int32_t cardIndex, int32_t module, naibrd_dif_pattern_ctrl_t controlBit, naibrd_dif_enable_t *outstate)
	Gets the state for the RAM Pattern Generator for the selected control bit on the module. Options are enable and disable.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetPatternGenBuf (int32_t cardIndex, int32_t module, int32_t dataPatternLen, uint32_t *dataPattern)
	Sets the pattern for RAM Pattern Generator.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetPatternGenBuf (int32_t cardIndex, int32_t module, int32_t dataPatternLen, uint32_t *dataPattern)
	Retrieves the pattern for RAM Pattern Generator.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetPatternGenCtrlRaw (int32_t cardIndex, int32_t module, uint32_t controlRaw)
	Sets the control bits for RAM Pattern Generator.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetPatternGenCtrlRaw (int32_t cardIndex, int32_t module, uint32_t *outcontrolRaw)
	Retrieves the control bits for RAM Pattern Generator.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetTimebaseInterval (int32_t cardIndex, int32_t module, int32_t channel, float64_t interval)
	Sets the timebase for frequency measurements for the specified Discrete channel.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetTimebaseInterval (int32_t cardIndex, int32_t module, int32_t channel, float64_t *outinterval)
	Retrieves the timebase for frequency measurements for the specified Discrete channel.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_ReadFIFORaw (int32_t cardIndex, int32_t module, int32_t channel, uint32_t count, uint32_t outdata[], uint32_t *outread)
	Retrieves the data elements from the Discrete channel's FIFO buffer.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_ReadFIFORawEx (int32_t cardIndex, int32_t module, int32_t channel, uint32_t count, uint32_t timeout, uint32_t outdata[], uint32_t outread, uint32_t countremaining)
	Retrieves the data elements from the Discrete channel's FIFO buffer.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetCountData (int32_t cardIndex, int32_t module, int32_t channel, uint32_t *outcount)
	Retrieves the measurement count data for the specified Discrete channel.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetFIFOCount (int32_t cardIndex, int32_t module, int32_t channel, uint32_t *outcount)
	Retrieves the number of elements in FIFO for the specified Discrete channel.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_ClearCountData (int32_t cardIndex, int32_t module, int32_t channel)
	Clears the measurement count data for the specified Discrete channel.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_ClearFIFO (int32_t cardIndex, int32_t module, int32_t channel)
	Clears the FIFO Data for the specified Discrete channel.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetFIFOStatus (int32_t cardIndex, int32_t module, int32_t channel, uint32_t outcount, naibrd_dif_fifo_status_t outstatus)
	Retrieves the Discrete channel's FIFO Buffer Status.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_ConvertToDebounceLSBtime (uint32_t modid, naibrd_dif_debounce_idx_t index, float64_t *debounceLSBtime)
	Returns the debounce LSB time value associated with the debounce LSB index.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_ConvertDebounceLSBtime (uint32_t modid, float64_t debounceLSBtime, uint32_t *debounceLSB)
	Returns the closest debounce LSB index associated with the debounce LSB time value parameter.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetRaw (int32_t cardIndex, int32_t module, naibrd_dif_raw_module_t type, uint32_t rawdata)
	Sets the raw data value in the register associated to the register type specified.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetRaw (int32_t cardIndex, int32_t module, naibrd_dif_raw_module_t type, uint32_t *outrawdata)
	Retrieves the raw data value in the register associated to the register type specified.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_SetChannelRaw (int32_t cardIndex, int32_t module, int32_t channel, naibrd_dif_raw_channel_t type, uint32_t rawdata)
	Sets the raw data value in the register associated to the channel and register type specified.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetChannelRaw (int32_t cardIndex, int32_t module, int32_t channel, naibrd_dif_raw_channel_t type, uint32_t *outrawdata)
	Retrieves the raw data value in the register associated to the channel and register type specified.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_GetChanMappedStatusRaw (int32_t cardIndex, int32_t module, naibrd_dif_chan_mapped_status_type_t type, uint32_t *outrawStatus)
	Retrieves the status for the specified DF1 channel and status type.

NAIBRDFUNC nai_status_t NAIAPI	naibrd_DIF_ClearChanMappedStatusRaw (int32_t cardIndex, int32_t module, naibrd_dif_chan_mapped_status_type_t type, uint32_t statusRaw)
	Clears the latched status for the specified DIF channel and status type.

Variables
static uint32_t	DIF_GEN3_DebounceTimeRegAddr [] = NAI_DIF_GEN3_REG_DEBOUNCE_TIME_ADD

static uint32_t	DIF_GEN3_IOFormatRegAddr [2] = NAI_DIF_GEN3_REG_INPUT_OUTPUT_FORMAT_ADD

static uint32_t	DIF_GEN3_DebounceLSBRegAddr [1] = { NAI_DIF_GEN3_REG_DEBOUNCE_LSB_ADD}

static uint32_t	DIF_GEN3_OutputStateRegAddr [1] = { NAI_DIF_GEN3_REG_WRITE_OUTPUT_ADD }

static uint32_t	DIF_GEN3_InputTerminationRegAddr [1] = { NAI_DIF_GEN3_REG_INPUT_TERMINATION_ADD }

static uint32_t	DIF_GEN3_SlewRateRegAddr [1] = { NAI_DIF_GEN3_REG_SLEW_RATE_ADD}

static uint32_t	DIF_GEN3_StatusRegAddr [NAIBRD_DIF_STATUS_TYPE_ENUM_COUNT]

static uint32_t	DIF_GEN3_IntEnableRegAddr [NAIBRD_DIF_STATUS_TYPE_ENUM_COUNT]

static uint32_t	DIF_GEN3_IntVectorRegAddr [NAIBRD_DIF_STATUS_TYPE_ENUM_COUNT]

static const uint32_t *const	DIF_GEN3_reg_module_raw [NAIBRD_DIF_RAW_MODULE_TYPE_ENUM_COUNT]

static const uint32_t *const	DIF_GEN3_reg_channel_raw [NAIBRD_DIF_RAW_CHAN_TYPE_ENUM_COUNT]

static float64_t	dif_gen3_debounceLSBtime [MAX_DIF_GEN3_DEBOUNCE_LSB_IDX_COUNT]

static uint32_t	DIF_GEN5_DebounceTimeRegAddr [] = NAI_DIF_GEN5_REG_DEBOUNCE_TIME_ADD

static uint32_t	DIF_GEN5_EnhancedModeSelectAddr [] = NAI_DIF_GEN5_REG_MODE_SELECT_ADD

static uint32_t	DIF_GEN5_OutputStateRegAddr [1] = { NAI_DIF_GEN5_REG_WRITE_OUTPUT_ADD }

static uint32_t	DIF_GEN5_InputTerminationRegAddr [1] = { NAI_DIF_GEN5_REG_INPUT_TERMINATION_ADD }

static uint32_t	DIF_GEN5_SlewRateRegAddr [1] = { NAI_DIF_GEN5_REG_SLEW_RATE_ADD}

static uint32_t	DIF_GEN5_Reg_Reset_Overcurrent [1] = { NAI_DIF_GEN5_REG_RESET_OVERCURRENT_ADD }

static uint32_t	DIF_GEN5_IOFormatRegAddr [1] = { NAI_DIF_GEN5_REG_INPUT_OUTPUT_FORMAT_ADD }

static uint32_t	DIF_GEN5_StatusRegAddr [NAIBRD_DIF_STATUS_TYPE_ENUM_COUNT]

static uint32_t	DIF_GEN5_IntEnableRegAddr [NAIBRD_DIF_STATUS_TYPE_ENUM_COUNT]

static uint32_t	DIF_GEN5_IntTypeRegAddr [NAIBRD_DIF_STATUS_TYPE_ENUM_COUNT]

static uint32_t	DIF_GEN5_InterruptNum [NAIBRD_DIF_STATUS_TYPE_ENUM_COUNT]

static uint32_t	DIF_LP1_InterruptNum [NAI_DIF_STATUS_TYPE_ENUM_COUNT]

static const uint32_t	DIF_GEN5_PWMPolarityRegAddr [1] = { NAI_DIF_GEN5_PWM_POLARITY_SELECT_ADD }

static const uint32_t	DIF_GEN5_PWM_PeriodRegAddr [16] = NAI_DIF_GEN5_REG_PWM_PERIOD_ADD

static const uint32_t	DIF_GEN5_PWM_PulseWidthRegAddr [16] = NAI_DIF_GEN5_REG_PWM_PULSEWIDTH_ADD

static const uint32_t	DIF_GEN5_PWM_BurstCountRegAddr [16] = NAI_DIF_GEN5_REG_PWM_BURST_COUNT_ADD

static const uint32_t	DIF_GEN5_FIFO_ResetRegAddr [1] = { NAI_DIF_GEN5_REG_RESET_FIFO_ADD }

static const uint32_t	DIF_GEN5_FIFO_DataRegAddr [16] = NAI_DIF_GEN5_REG_FIFO_DATA_ADD

static const uint32_t	DIF_GEN5_FIFO_StatusRegAddr [16] = NAI_DIF_GEN5_REG_FIFO_STATUS_ADD

static const uint32_t	DIF_GEN5_CountDataRegAddr [16] = NAI_DIF_GEN5_REG_COUNT_DATA_ADD

static const uint32_t	DIF_GEN5_TimebaseIntervalRegAddr [16] = NAI_DIF_GEN5_REG_TIMEBASE_INTERVAL_ADD

static const uint32_t	DIF_GEN5_CountDataResetRegAddr [1] = { NAI_DIF_GEN5_REG_RESET_TIMER_ADD }

static const uint32_t	DIF_GEN5_FIFO_CountRegAddr [16] = NAI_DIF_GEN5_REG_COUNT_ADD

static const uint32_t	DIF_GEN5_EnhancedModeMappedVal [] = NAI_DIF_GEN5_MODE_MAPPED_VALUE

static const uint32_t *const	DIF_GEN5_reg_module_raw [NAIBRD_DIF_RAW_MODULE_TYPE_ENUM_COUNT]

static const uint32_t *const	DIF_GEN5_reg_channel_raw [NAIBRD_DIF_RAW_CHAN_TYPE_ENUM_COUNT]

static const uint32_t *const	df2_gen5_reg_chan_raw [NAIBRD_DIF_RAW_CHAN_TYPE_ENUM_COUNT]

Function Documentation

◆ GetChannelCount()

static int32_t GetChannelCount ( uint32_t modid )

static

◆ GetFIFOInfo()

static nai_status_t GetFIFOInfo	(	int32_t	cardIndex,
		int32_t	module,
		int32_t	channel,
		uint32_t	modid,
		uint32_t *	outcount,
		naibrd_dif_fifo_status_t *	outstatus )

static

◆ GetGroupCount()

static int32_t GetGroupCount ( uint32_t modid )

static

◆ GetGroupSize()

static int32_t GetGroupSize ( uint32_t modid )

static

◆ naibrd_DIF_GetFIFOCount()

NAIBRDFUNC nai_status_t NAIAPI naibrd_DIF_GetFIFOCount	(	int32_t	cardIndex,
		int32_t	module,
		int32_t	channel,
		uint32_t *	outcount )

Retrieves the number of elements in FIFO for the specified Discrete channel.

Parameters

cardIndex	: (Input) Logical Card Index assigned to connection with the NAI_BOARD (0 - NAI_MAX_CARDS-1).
module	: (Input) Module Number of the module to access (1 - [max modules for board]).
channel	: (Input) Channel Number of the channel to access (1 - [max channels for module]).
outcount	: (Output) number of elements in Discrete channel FIFO .

NAI_SUCCESS
NAI_ERROR_INVALID_CARD when invalid card parameter is specified.
NAI_ERROR_INVALID_MODULE when invalid card parameter is specified.
NAI_ERROR_INVALID_CHANNEL when invalid channel parameter is specified.
NAI_ERROR_NOT_OPEN when handle to board is invalid.
NAI_ERROR_NOT_SUPPORTED when function is not supported.

◆ naibrd_DIF_verify_burstnum()

static nai_status_t naibrd_DIF_verify_burstnum ( int32_t burstnum )

static

◆ naibrd_DIF_verify_chan_mapped_status_type()

static nai_status_t naibrd_DIF_verify_chan_mapped_status_type ( naibrd_dif_chan_mapped_status_type_t type )

static

◆ naibrd_DIF_verify_channel()

static nai_status_t naibrd_DIF_verify_channel	(	uint32_t	modid,
		int32_t	channel )

static

◆ naibrd_DIF_verify_debounce_idx_type()

static nai_status_t naibrd_DIF_verify_debounce_idx_type	(	int32_t	modid,
		naibrd_dif_debounce_idx_t	type )

static

◆ naibrd_DIF_verify_enable_type()

static nai_status_t naibrd_DIF_verify_enable_type ( naibrd_dif_enable_t type )

static

◆ naibrd_DIF_verify_enhaced_mode_type()

static nai_status_t naibrd_DIF_verify_enhaced_mode_type ( naibrd_dif_enhanced_mode_t mode )

static

◆ naibrd_DIF_verify_pattern_control_type()

static nai_status_t naibrd_DIF_verify_pattern_control_type ( naibrd_dif_pattern_ctrl_t type )

static

◆ naibrd_DIF_verify_pattern_length_type()

static nai_status_t naibrd_DIF_verify_pattern_length_type ( int32_t dataPatternLen )

static

◆ naibrd_DIF_verify_pwm_polarity_type()

static nai_status_t naibrd_DIF_verify_pwm_polarity_type ( naibrd_dif_pwm_polarity_t type )

static

◆ naibrd_DIF_verify_raw_channel_type()

static nai_status_t naibrd_DIF_verify_raw_channel_type ( naibrd_dif_raw_channel_t type )

static

◆ naibrd_DIF_verify_raw_module_type()

static nai_status_t naibrd_DIF_verify_raw_module_type ( naibrd_dif_raw_module_t type )

static

◆ naibrd_DIF_verify_reset_type()

static nai_status_t naibrd_DIF_verify_reset_type ( naibrd_dif_reset_type_t type )

static

◆ naibrd_DIF_verify_timebase_values()

static nai_status_t naibrd_DIF_verify_timebase_values	(	uint32_t	modid,
		float64_t	time )

static

Variable Documentation

◆ df2_gen5_reg_chan_raw

const uint32_t* const df2_gen5_reg_chan_raw[NAIBRD_DIF_RAW_CHAN_TYPE_ENUM_COUNT]

static

Initial value:

=
{
   DIF_GEN5_DebounceTimeRegAddr,
   DIF_GEN5_PWM_PeriodRegAddr,
   DIF_GEN5_PWM_PulseWidthRegAddr,
   DIF_GEN5_PWM_BurstCountRegAddr,
   DIF_GEN5_EnhancedModeSelectAddr
}

◆ DIF_GEN3_DebounceLSBRegAddr

uint32_t DIF_GEN3_DebounceLSBRegAddr[1] = { NAI_DIF_GEN3_REG_DEBOUNCE_LSB_ADD}

static

◆ dif_gen3_debounceLSBtime

float64_t dif_gen3_debounceLSBtime[MAX_DIF_GEN3_DEBOUNCE_LSB_IDX_COUNT]

static

Initial value:

◆ DIF_GEN3_DebounceTimeRegAddr

uint32_t DIF_GEN3_DebounceTimeRegAddr[] = NAI_DIF_GEN3_REG_DEBOUNCE_TIME_ADD

static

◆ DIF_GEN3_InputTerminationRegAddr

uint32_t DIF_GEN3_InputTerminationRegAddr[1] = { NAI_DIF_GEN3_REG_INPUT_TERMINATION_ADD }

static

◆ DIF_GEN3_IntEnableRegAddr

uint32_t DIF_GEN3_IntEnableRegAddr[NAIBRD_DIF_STATUS_TYPE_ENUM_COUNT]

static

Initial value:

= {
   NAI_DIF_GEN3_REG_BIT_INT_ENABLE_ADD,
   0,
   NAI_DIF_GEN3_REG_OVERCURRENT_INT_ENABLE_ADD,
   0,
   NAI_DIF_GEN3_REG_LO_HI_TRANS_INT_ENABLE_ADD,
   0,
   NAI_DIF_GEN3_REG_HI_LO_TRANS_INT_ENABLE_ADD,
   0,
   0,
   0
}

◆ DIF_GEN3_IntVectorRegAddr

uint32_t DIF_GEN3_IntVectorRegAddr[NAIBRD_DIF_STATUS_TYPE_ENUM_COUNT]

static

Initial value:

= {
   NAI_DIF_GEN3_REG_BIT_INT_VECTOR_ADD,
   0,
   NAI_DIF_GEN3_REG_OVERCURRENT_INT_VECTOR_ADD,
   0,
   NAI_DIF_GEN3_REG_LO_HI_TRANS_INT_VECTOR_ADD,
   0,
   NAI_DIF_GEN3_REG_HI_LO_TRANS_INT_VECTOR_ADD,
   0,
   0,
   0
}

◆ DIF_GEN3_IOFormatRegAddr

uint32_t DIF_GEN3_IOFormatRegAddr[2] = NAI_DIF_GEN3_REG_INPUT_OUTPUT_FORMAT_ADD

static

◆ DIF_GEN3_OutputStateRegAddr

uint32_t DIF_GEN3_OutputStateRegAddr[1] = { NAI_DIF_GEN3_REG_WRITE_OUTPUT_ADD }

static

◆ DIF_GEN3_reg_channel_raw

const uint32_t* const DIF_GEN3_reg_channel_raw[NAIBRD_DIF_RAW_CHAN_TYPE_ENUM_COUNT]

static

Initial value:

=
{
   DIF_GEN3_DebounceTimeRegAddr,
   NULL,
   NULL,
   NULL,
   NULL
}

◆ DIF_GEN3_reg_module_raw

const uint32_t* const DIF_GEN3_reg_module_raw[NAIBRD_DIF_RAW_MODULE_TYPE_ENUM_COUNT]

static

Initial value:

= {
   DIF_GEN3_DebounceLSBRegAddr,
   NULL,
   DIF_GEN3_SlewRateRegAddr,
   DIF_GEN3_InputTerminationRegAddr,
   DIF_GEN3_OutputStateRegAddr,
   DIF_GEN3_IOFormatRegAddr
}

◆ DIF_GEN3_SlewRateRegAddr

uint32_t DIF_GEN3_SlewRateRegAddr[1] = { NAI_DIF_GEN3_REG_SLEW_RATE_ADD}

static

◆ DIF_GEN3_StatusRegAddr

uint32_t DIF_GEN3_StatusRegAddr[NAIBRD_DIF_STATUS_TYPE_ENUM_COUNT]

static

Initial value:

= {
   NAI_DIF_GEN3_REG_BIT_LATCHED_STATUS_ADD,
   0,
   NAI_DIF_GEN3_REG_OVERCURRENT_LATCHED_STATUS_ADD,
   0,
   NAI_DIF_GEN3_REG_LO_HI_TRANS_LATCHED_STATUS_ADD,
   0,
   NAI_DIF_GEN3_REG_HI_LO_TRANS_LATCHED_STATUS_ADD,
   0,
   0,
   0
}

◆ DIF_GEN5_CountDataRegAddr

const uint32_t DIF_GEN5_CountDataRegAddr[16] = NAI_DIF_GEN5_REG_COUNT_DATA_ADD

static

◆ DIF_GEN5_CountDataResetRegAddr

const uint32_t DIF_GEN5_CountDataResetRegAddr[1] = { NAI_DIF_GEN5_REG_RESET_TIMER_ADD }

static

◆ DIF_GEN5_DebounceTimeRegAddr

uint32_t DIF_GEN5_DebounceTimeRegAddr[] = NAI_DIF_GEN5_REG_DEBOUNCE_TIME_ADD

static

◆ DIF_GEN5_EnhancedModeMappedVal

const uint32_t DIF_GEN5_EnhancedModeMappedVal[] = NAI_DIF_GEN5_MODE_MAPPED_VALUE

static

◆ DIF_GEN5_EnhancedModeSelectAddr

uint32_t DIF_GEN5_EnhancedModeSelectAddr[] = NAI_DIF_GEN5_REG_MODE_SELECT_ADD

static

◆ DIF_GEN5_FIFO_CountRegAddr

const uint32_t DIF_GEN5_FIFO_CountRegAddr[16] = NAI_DIF_GEN5_REG_COUNT_ADD

static

◆ DIF_GEN5_FIFO_DataRegAddr

const uint32_t DIF_GEN5_FIFO_DataRegAddr[16] = NAI_DIF_GEN5_REG_FIFO_DATA_ADD

static

◆ DIF_GEN5_FIFO_ResetRegAddr

const uint32_t DIF_GEN5_FIFO_ResetRegAddr[1] = { NAI_DIF_GEN5_REG_RESET_FIFO_ADD }

static

◆ DIF_GEN5_FIFO_StatusRegAddr

const uint32_t DIF_GEN5_FIFO_StatusRegAddr[16] = NAI_DIF_GEN5_REG_FIFO_STATUS_ADD

static

◆ DIF_GEN5_InputTerminationRegAddr

uint32_t DIF_GEN5_InputTerminationRegAddr[1] = { NAI_DIF_GEN5_REG_INPUT_TERMINATION_ADD }

static

◆ DIF_GEN5_IntEnableRegAddr

uint32_t DIF_GEN5_IntEnableRegAddr[NAIBRD_DIF_STATUS_TYPE_ENUM_COUNT]

static

Initial value:

= {
   NAI_DIF_GEN5_REG_BIT_INT_ENABLE_ADD,
   0,
   NAI_DIF_GEN5_REG_OVERCURRENT_INT_ENABLE_ADD,
   0,
   NAI_DIF_GEN5_REG_LO_HI_TRANS_INT_ENABLE_ADD,
   0,
   NAI_DIF_GEN5_REG_HI_LO_TRANS_INT_ENABLE_ADD,
   0,
   NAI_DIF_CTS_GEN5_REG_RUNSTATUS_INT_ENABLE_ADD,
   0
}

◆ DIF_GEN5_InterruptNum

uint32_t DIF_GEN5_InterruptNum[NAIBRD_DIF_STATUS_TYPE_ENUM_COUNT]

static

Initial value:

= {
   NAI_DIF_GEN5_REG_BIT_INT_VECTOR_STEERING_INTNUM,                
   NAI_DIF_GEN5_REG_BIT_INT_VECTOR_STEERING_INTNUM,                
   NAI_DIF_GEN5_REG_OVERCURRENT_INT_VECTOR_STEERING_INTNUM,        
   NAI_DIF_GEN5_REG_OVERCURRENT_INT_VECTOR_STEERING_INTNUM,        
   NAI_DIF_GEN5_REG_LO_HI_TRANS_INT_VECTOR_STEERING_INTNUM,       
   NAI_DIF_GEN5_REG_LO_HI_TRANS_INT_VECTOR_STEERING_INTNUM,       
   NAI_DIF_GEN5_REG_HI_LO_TRANS_INT_VECTOR_STEERING_INTNUM,       
   NAI_DIF_GEN5_REG_HI_LO_TRANS_INT_VECTOR_STEERING_INTNUM,       
   NAI_DIF_CTS_GEN5_REG_RUNSTATUS_INT_VECTOR_STEERING_INTNUM,     
   NAI_DIF_CTS_GEN5_REG_RUNSTATUS_INT_VECTOR_STEERING_INTNUM      
}

◆ DIF_GEN5_IntTypeRegAddr

uint32_t DIF_GEN5_IntTypeRegAddr[NAIBRD_DIF_STATUS_TYPE_ENUM_COUNT]

static

Initial value:

= {
   NAI_DIF_GEN5_REG_BIT_EDGE_LEVEL_INT_ADD,
   NAI_DIF_GEN5_REG_BIT_EDGE_LEVEL_INT_ADD,
   NAI_DIF_GEN5_REG_OVERCURRENT_EDGE_LEVEL_INT_ADD,
   NAI_DIF_GEN5_REG_OVERCURRENT_EDGE_LEVEL_INT_ADD,
   NAI_DIF_GEN5_REG_LO_HI_TRANS_EDGE_LEVEL_INT_ADD,
   NAI_DIF_GEN5_REG_LO_HI_TRANS_EDGE_LEVEL_INT_ADD,
   NAI_DIF_GEN5_REG_HI_LO_TRANS_EDGE_LEVEL_INT_ADD,
   NAI_DIF_GEN5_REG_HI_LO_TRANS_EDGE_LEVEL_INT_ADD,
   NAI_DIF_CTS_GEN5_REG_RUNSTATUS_EDGE_LEVEL_INT_ADD,
   NAI_DIF_CTS_GEN5_REG_RUNSTATUS_EDGE_LEVEL_INT_ADD
}

◆ DIF_GEN5_IOFormatRegAddr

uint32_t DIF_GEN5_IOFormatRegAddr[1] = { NAI_DIF_GEN5_REG_INPUT_OUTPUT_FORMAT_ADD }

static

◆ DIF_GEN5_OutputStateRegAddr

uint32_t DIF_GEN5_OutputStateRegAddr[1] = { NAI_DIF_GEN5_REG_WRITE_OUTPUT_ADD }

static

◆ DIF_GEN5_PWM_BurstCountRegAddr

const uint32_t DIF_GEN5_PWM_BurstCountRegAddr[16] = NAI_DIF_GEN5_REG_PWM_BURST_COUNT_ADD

static

◆ DIF_GEN5_PWM_PeriodRegAddr

const uint32_t DIF_GEN5_PWM_PeriodRegAddr[16] = NAI_DIF_GEN5_REG_PWM_PERIOD_ADD

static

◆ DIF_GEN5_PWM_PulseWidthRegAddr

const uint32_t DIF_GEN5_PWM_PulseWidthRegAddr[16] = NAI_DIF_GEN5_REG_PWM_PULSEWIDTH_ADD

static

◆ DIF_GEN5_PWMPolarityRegAddr

const uint32_t DIF_GEN5_PWMPolarityRegAddr[1] = { NAI_DIF_GEN5_PWM_POLARITY_SELECT_ADD }

static

◆ DIF_GEN5_reg_channel_raw

const uint32_t* const DIF_GEN5_reg_channel_raw[NAIBRD_DIF_RAW_CHAN_TYPE_ENUM_COUNT]

static

Initial value:

=
{
   DIF_GEN5_DebounceTimeRegAddr,
   NULL,
   NULL,
   NULL,
   NULL
}

◆ DIF_GEN5_reg_module_raw

const uint32_t* const DIF_GEN5_reg_module_raw[NAIBRD_DIF_RAW_MODULE_TYPE_ENUM_COUNT]

static

Initial value:

= {
   NULL,
   DIF_GEN5_PWMPolarityRegAddr,
   DIF_GEN5_SlewRateRegAddr,
   DIF_GEN5_InputTerminationRegAddr,
   DIF_GEN5_OutputStateRegAddr,
   DIF_GEN5_IOFormatRegAddr
}

◆ DIF_GEN5_Reg_Reset_Overcurrent

uint32_t DIF_GEN5_Reg_Reset_Overcurrent[1] = { NAI_DIF_GEN5_REG_RESET_OVERCURRENT_ADD }

static

◆ DIF_GEN5_SlewRateRegAddr

uint32_t DIF_GEN5_SlewRateRegAddr[1] = { NAI_DIF_GEN5_REG_SLEW_RATE_ADD}

static

◆ DIF_GEN5_StatusRegAddr

uint32_t DIF_GEN5_StatusRegAddr[NAIBRD_DIF_STATUS_TYPE_ENUM_COUNT]

static

Initial value:

= {
   NAI_DIF_GEN5_REG_BIT_LATCHED_STATUS_ADD,
   NAI_DIF_GEN5_REG_BIT_REALTIME_STATUS_ADD,
   NAI_DIF_GEN5_REG_OVERCURRENT_LATCHED_STATUS_ADD,
   NAI_DIF_GEN5_REG_OVERCURRENT_REALTIME_STATUS_ADD,
   NAI_DIF_GEN5_REG_LO_HI_TRANS_LATCHED_STATUS_ADD,
   NAI_DIF_GEN5_REG_LO_HI_TRANS_REALTIME_STATUS_ADD,
   NAI_DIF_GEN5_REG_HI_LO_TRANS_LATCHED_STATUS_ADD,
   NAI_DIF_GEN5_REG_HI_LO_TRANS_REALTIME_STATUS_ADD,
   NAI_DIF_CTS_GEN5_REG_RUNSTATUS_LATCHED_STATUS_ADD,
   NAI_DIF_CTS_GEN5_REG_RUNSTATUS_REALTIME_STATUS_ADD
}

◆ DIF_GEN5_TimebaseIntervalRegAddr

const uint32_t DIF_GEN5_TimebaseIntervalRegAddr[16] = NAI_DIF_GEN5_REG_TIMEBASE_INTERVAL_ADD

static

◆ DIF_LP1_InterruptNum

uint32_t DIF_LP1_InterruptNum[NAI_DIF_STATUS_TYPE_ENUM_COUNT]

static

Initial value:

= {
   NAI_DIF_LP1_REG_BIT_INT_VECTOR_STEERING_INTNUM,                
   NAI_DIF_LP1_REG_BIT_INT_VECTOR_STEERING_INTNUM,                
   NAI_DIF_LP1_REG_OVERCURRENT_INT_VECTOR_STEERING_INTNUM,        
   NAI_DIF_LP1_REG_OVERCURRENT_INT_VECTOR_STEERING_INTNUM,        
   NAI_DIF_LP1_REG_LO_HI_TRANS_INT_VECTOR_STEERING_INTNUM,        
   NAI_DIF_LP1_REG_LO_HI_TRANS_INT_VECTOR_STEERING_INTNUM,        
   NAI_DIF_LP1_REG_HI_LO_TRANS_INT_VECTOR_STEERING_INTNUM,        
   NAI_DIF_LP1_REG_HI_LO_TRANS_INT_VECTOR_STEERING_INTNUM,        
   NAI_DIF_CTS_GEN5_REG_RUNSTATUS_INT_VECTOR_STEERING_INTNUM,     
   NAI_DIF_CTS_GEN5_REG_RUNSTATUS_INT_VECTOR_STEERING_INTNUM      
}

Functions

Variables

Function Documentation

◆ GetChannelCount()

◆ GetFIFOInfo()

◆ GetGroupCount()

◆ GetGroupSize()

◆ naibrd_DIF_GetFIFOCount()

◆ naibrd_DIF_verify_burstnum()

◆ naibrd_DIF_verify_chan_mapped_status_type()

◆ naibrd_DIF_verify_channel()

◆ naibrd_DIF_verify_debounce_idx_type()

◆ naibrd_DIF_verify_enable_type()

◆ naibrd_DIF_verify_enhaced_mode_type()

◆ naibrd_DIF_verify_pattern_control_type()

◆ naibrd_DIF_verify_pattern_length_type()

◆ naibrd_DIF_verify_pwm_polarity_type()

◆ naibrd_DIF_verify_raw_channel_type()

◆ naibrd_DIF_verify_raw_module_type()

◆ naibrd_DIF_verify_reset_type()

◆ naibrd_DIF_verify_timebase_values()

Variable Documentation

◆ df2_gen5_reg_chan_raw

◆ DIF_GEN3_DebounceLSBRegAddr

◆ dif_gen3_debounceLSBtime

◆ DIF_GEN3_DebounceTimeRegAddr

◆ DIF_GEN3_InputTerminationRegAddr

◆ DIF_GEN3_IntEnableRegAddr

◆ DIF_GEN3_IntVectorRegAddr

◆ DIF_GEN3_IOFormatRegAddr

◆ DIF_GEN3_OutputStateRegAddr

◆ DIF_GEN3_reg_channel_raw

◆ DIF_GEN3_reg_module_raw

◆ DIF_GEN3_SlewRateRegAddr

◆ DIF_GEN3_StatusRegAddr

◆ DIF_GEN5_CountDataRegAddr

◆ DIF_GEN5_CountDataResetRegAddr

◆ DIF_GEN5_DebounceTimeRegAddr

◆ DIF_GEN5_EnhancedModeMappedVal

◆ DIF_GEN5_EnhancedModeSelectAddr

◆ DIF_GEN5_FIFO_CountRegAddr

◆ DIF_GEN5_FIFO_DataRegAddr

◆ DIF_GEN5_FIFO_ResetRegAddr

◆ DIF_GEN5_FIFO_StatusRegAddr

◆ DIF_GEN5_InputTerminationRegAddr

◆ DIF_GEN5_IntEnableRegAddr

◆ DIF_GEN5_InterruptNum

◆ DIF_GEN5_IntTypeRegAddr

◆ DIF_GEN5_IOFormatRegAddr

◆ DIF_GEN5_OutputStateRegAddr

◆ DIF_GEN5_PWM_BurstCountRegAddr

◆ DIF_GEN5_PWM_PeriodRegAddr

◆ DIF_GEN5_PWM_PulseWidthRegAddr

◆ DIF_GEN5_PWMPolarityRegAddr

◆ DIF_GEN5_reg_channel_raw

◆ DIF_GEN5_reg_module_raw

◆ DIF_GEN5_Reg_Reset_Overcurrent

◆ DIF_GEN5_SlewRateRegAddr

◆ DIF_GEN5_StatusRegAddr

◆ DIF_GEN5_TimebaseIntervalRegAddr

◆ DIF_LP1_InterruptNum